Design and FPGA Implementation of an Efficient Architecture for Noise Removal in ECG Signals Using Lifting-Based Wavelet Denoising

Noise removal is the most crucial pre-processing step for present-generation biomedical wearable electrocardiogram (ECG) patches and devices to provide efficient detection and monitoring of cardiac arrhythmias. This paper proposes a hardware-efficient and multiplier-less FPGA-based ECG noise removal...

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Vydáno v:2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC) Ročník 1; s. 1 - 6
Hlavní autoři: Gon, Anusaka, Mukherjee, Atin
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 04.05.2023
Témata:
Computer architecture
Discrete wavelet transforms
ECG noise removal
Electrocardiography
Field programmable gate arrays
Field programming gate array
lifting-based discrete wavelet transform
Noise reduction
Resource management
soft thresholding
wearable ECG devices
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Shrnutí:Noise removal is the most crucial pre-processing step for present-generation biomedical wearable electrocardiogram (ECG) patches and devices to provide efficient detection and monitoring of cardiac arrhythmias. This paper proposes a hardware-efficient and multiplier-less FPGA-based ECG noise removal architecture based on lifting-based wavelet denoising that employs a universal threshold level-dependent function in combination with soft thresholding to produce a noise-free ECG signal. The paper also proposes a modified lifting-based discrete wavelet transform (DWT) algorithm that is multiplier-less and provides a one-step equation for the calculation of the forward output coefficients and the inverse output coefficients. Since a comparator circuit is a very complicated circuitry in VLSI implementation, an optimized median calculation and soft thresholding block with no compare operations for wavelet-based thresholding is proposed. The ECG data is collected from the MIT-BIH arrhythmia database and the ECG noises from the MIT-BIH noise stress database. The proposed denoising technique for the ECG signal is tested on MATLAB which achieves an average improvement in SNR of 7.4 dB and an MSE of 0.0206. The FPGA implementation is performed on the Nexys 4 DDR board, and the proposed wavelet-based denoising architecture results in lower hardware utilization and a relatively high operating frequency of 166 MHz when compared to existing ECG denoising architectures.
DOI:10.1109/ESDC56251.2023.10149865