Design and optimization of power management circuits for low-power VLSI systems

This study delves into the topic of low-power VLSI system power management circuit design and optimization. The purpose of this research is to learn what influences VLSI circuits' power consumption and how to minimize that effect in low-power VLSI designs. Using multiple linear regression analy...

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Veröffentlicht in:2023 International Conference on Innovative Computing, Intelligent Communication and Smart Electrical Systems (ICSES) S. 1 - 5
Hauptverfasser: Ramashri, T., Christy, A. Ananthi, Abdul Munaf, K, Gowri, V., Ramesh, D. Raja, Deivakani, M.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 14.12.2023
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Zusammenfassung:This study delves into the topic of low-power VLSI system power management circuit design and optimization. The purpose of this research is to learn what influences VLSI circuits' power consumption and how to minimize that effect in low-power VLSI designs. Using multiple linear regression analysis, this research determines that capacitance, frequency, voltage and temperature are all important predictors of power usage in VLSI circuits. The study's findings may be utilized to guide the creation of novel power management strategies and technologies, with significant implications for the design and optimization of power management circuits in low-power VLSI systems. New materials and technologies for VLSI systems, as well as improved power management strategies, are only two examples of where the report proposes future research should go. This study's findings have significant significance for a broad variety of applications, including embedded systems, mobile devices and IoT gadgets, since they provide light on the design and optimization of power management circuits for low-power VLSI systems.
DOI:10.1109/ICSES60034.2023.10465447