Radix-3 low-complexity modulo-M multipliers

This paper introduces a family of radix-3 modulo-M multipliers. Following the description of a high-radix modulo multiplication algorithm, a set of low-complexity digit adders are introduced and subsequently used to compose the proposed modulo multipliers. Complexity reduction of the particular digi...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:International Workshop on Power and Timing Modeling, Optimization and Simulation (Online) s. 107 - 112
Hlavní autoři: Kouretas, Ioannis, Paliouras, Vassilis
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.07.2019
Témata:
Adders
Complexity theory
Delays
design methodology
Hardware
high-radix arithmetic
Logic gates
Mathematical model
Optimization
residue multiplication
Residue Number System
ISSN:2643-3222
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:This paper introduces a family of radix-3 modulo-M multipliers. Following the description of a high-radix modulo multiplication algorithm, a set of low-complexity digit adders are introduced and subsequently used to compose the proposed modulo multipliers. Complexity reduction of the particular digit adders is achieved by exploiting the limited set of the possible values assumed by the inputs. The proposed modulo-M multipliers are derived by means of a graph-based optimization algorithm which selects the appropriate digit adders from a set of possible choices to produce minimal complexity solutions. The proposed multipliers are synthesized using a 0.18μm 1.8V CMOS standard-cell library. Comparisons to previously reported radix-2 and radix-3 modulo multipliers reveal that the proposed multipliers achieve complexity savings in terms of area, delay and area × delay complexities for certain moduli.
ISSN:2643-3222
DOI:10.1109/PATMOS.2019.8862036