Rate analysis for streaming applications with on-chip buffer constraints

While mapping a streaming (such as multimedia or network packet processing) application onto a specified architecture, an important issue is to determine the input stream rates that can be supported by the architecture for any given mapping. This is subject to typical constraints such as on-chip buf...

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Bibliographic Details
Published in:ASP-DAC 2004 : proceedings of the ASP-DAC 2004 Asia and South Pacific Design Automation Conference, 2004 : January 27-January 30, 2004, Pacifico Yokohama, Yokohama, Japan pp. 131 - 136
Main Authors: Maxiaguine, A., Kunzli, S., Samarjit Chakraborty, Thiele, L.
Format: Conference Proceeding
Language:English
Published: IEEE 2004
Subjects:
Buffer storage
Costs
Energy consumption
Feeds
Handheld computers
Mobile handsets
Network-on-a-chip
Streaming media
System-on-a-chip
ISBN:0780381750, 9780780381759
Online Access:Get full text
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Summary:While mapping a streaming (such as multimedia or network packet processing) application onto a specified architecture, an important issue is to determine the input stream rates that can be supported by the architecture for any given mapping. This is subject to typical constraints such as on-chip buffers should not overflow, and specified play out buffers (which feed audio or video devices) should not underflow, so that the quality of the audio/video output is maintained. The main difficulty in this problem arises from the high variability in execution times of stream processing algorithms, coupled with the bursty nature of the streams to be processed. We present a mathematical framework for such a rate analysis for streaming applications, and illustrate its feasibility through a detailed case study of a MPEG-2 decoder application. When integrated into a tool for automated design-space exploration, such an analysis can be used for fast performance evaluation of different stream processing architectures.
ISBN:0780381750
9780780381759
DOI:10.1109/ASPDAC.2004.1337553