A parallel architecture for video compression

This paper reports a parallel algorithm for compression/decompression of video data files. The algorithm can be easily implemented on a parallel pipelined architecture that can support on-line compression/decompression. The hardware implementing the architecture achieves a throughput of 30 frames pe...

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Veröffentlicht in:Proceedings Tenth International Conference on VLSI Design S. 247 - 252
Hauptverfasser: Bhattacharjee, S., Das, S., Saha, D., Chowdhury, D.R., Chaudhuri, P.P.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 1997
Schlagworte:
Data compression
Decoding
Hardware
Image sequences
Layout
Parallel architectures
Throughput
Transform coding
Very large scale integration
Video compression
ISBN:9780818677557, 0818677554
ISSN:1063-9667
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Beschreibung
Zusammenfassung:This paper reports a parallel algorithm for compression/decompression of video data files. The algorithm can be easily implemented on a parallel pipelined architecture that can support on-line compression/decompression. The hardware implementing the architecture achieves a throughput of 30 frames per second with frame size of 352/spl times/272 pixels.
ISBN:9780818677557
0818677554
ISSN:1063-9667
DOI:10.1109/ICVD.1997.568084