Circuit design techniques for a gigahertz integer microprocessor

Using highly optimized, custom circuits and fast dynamic array control structures, a small team of designers at the IBM Austin Research Laboratory has developed a one gigahertz microprocessor. This paper describes the custom datapath circuit technology employed in this design. Particular attention w...

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Veröffentlicht in:Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) S. 11 - 16
Hauptverfasser: Nowka, K.J., Galambos, T.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 1998
Schlagworte:
Circuit noise
Circuit synthesis
CMOS technology
Concurrent computing
Delay
Frequency
Laboratories
Logic arrays
Logic circuits
Microprocessors
ISBN:9780818690990, 0818690992
ISSN:1063-6404
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:Using highly optimized, custom circuits and fast dynamic array control structures, a small team of designers at the IBM Austin Research Laboratory has developed a one gigahertz microprocessor. This paper describes the custom datapath circuit technology employed in this design. Particular attention was paid in the design process to the trade-off between performance and noise-margins. To achieve the low circuit latencies, highly-optimized and noise-characterized delayed-reset domino circuits were employed in the datapath elements of the gigahertz design.
ISBN:9780818690990
0818690992
ISSN:1063-6404
DOI:10.1109/ICCD.1998.727017