Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications

Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications are presented. These (41, 32) codes allow fast single error correcting with three parity bit penalty and can be used in combinational circuits with minimal (ultimat...

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Bibliographic Details

Published in:	Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems pp. 308 - 313
Main Authors:	Amir, K., Eric, B.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 2001
Subjects:	Birth disorders Circuits Complexity theory Decoding Delay Encoding Error correction codes Power dissipation Random access memory System-on-a-chip
ISBN:	9780769512037, 0769512038
ISSN:	1550-5774
Online Access:	Get full text
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