Amir, K., & Eric, B. (2001). Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications. Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 308-313. https://doi.org/10.1109/DFTVS.2001.966783
Citace podle Chicago (17th ed.)Amir, K., a B. Eric. "Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-error-correcting Codes for On-chip DRAM Applications." Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2001: 308-313. https://doi.org/10.1109/DFTVS.2001.966783.
Citace podle MLA (9th ed.)Amir, K., a B. Eric. "Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-error-correcting Codes for On-chip DRAM Applications." Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 308-313, https://doi.org/10.1109/DFTVS.2001.966783.