Adaptive synchronization

Delay variations are typically accounted for by increasing cycle time margins. Adaptive synchronization eliminates this on inter-modular interfaces in very large, high performance chips. The chip is divided into multiple smaller synchronous modules. Multi-synchronous hierarchical clocking provides t...

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Bibliographic Details
Published in:Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) pp. 188 - 189
Main Authors: Ginosar, R., Kol, R.
Format: Conference Proceeding
Language:English
Published: IEEE 1998
Subjects:
Clocks
Delay effects
Frequency synchronization
ISBN:9780818690990, 0818690992
ISSN:1063-6404
Online Access:Get full text
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Summary:Delay variations are typically accounted for by increasing cycle time margins. Adaptive synchronization eliminates this on inter-modular interfaces in very large, high performance chips. The chip is divided into multiple smaller synchronous modules. Multi-synchronous hierarchical clocking provides the same frequency to all modules, but does not maintain any particular phase. Adaptive synchronizers adapt to the time-varying inter-modular clock and data phases, and out-perform conventional synchronizers.
ISBN:9780818690990
0818690992
ISSN:1063-6404
DOI:10.1109/ICCD.1998.727042