Asynchronous implementation of synchronous Esterel specifications

The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for...

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Veröffentlicht in:Proceedings Tenth International Conference on VLSI Design S. 348 - 353
Hauptverfasser: Mitra, R.S., Bhattacharya, B., Lavagno, L.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 1997
Schlagworte:
Broadcasting
Circuit synthesis
Delay
Embedded software
Embedded system
Hardware
Integrated circuit interconnections
Merging
Software systems
Very large scale integration
ISBN:9780818677557, 0818677554
ISSN:1063-9667
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Zusammenfassung:The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this translation algorithm so that the user is aware of the executable semantics that he should expect.
ISBN:9780818677557
0818677554
ISSN:1063-9667
DOI:10.1109/ICVD.1997.568106