Design and VLSI implementation of low power rational arithmetic unit
Computer arithmetic continues to be an important topic in computer architecture as the primary design focus shifts to mobile processors. Advances in computer architecture have allowed the performance of digital computer hardware to continue its exponential growth, despite increasing technological di...
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| Format: | Dissertation |
| Language: | English |
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ProQuest Dissertations & Theses
01.01.2012
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| ISBN: | 9781267346551, 1267346558 |
| Online Access: | Get full text |
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| Summary: | Computer arithmetic continues to be an important topic in computer architecture as the primary design focus shifts to mobile processors. Advances in computer architecture have allowed the performance of digital computer hardware to continue its exponential growth, despite increasing technological difficulty in speed improvement at the circuit level. Generally battery operated, mobile integrated circuits are required to consume as little power as possible. The increased leakage power dissipation in sub-65 nm technology node is a great burden on power constraint of mobile chip design. Furthermore, most work load of these chips are in application areas such as digital signal processing, multimedia and graphics that requires extensive numerical and fractional computation. In mathematics, a rational number is any number that can be expressed as the quotient or fraction a/b of two integers, with the denominator b not equal to zero. Rational approximation is widely known to offer efficient algorithms to compute rational functions. In this research a low power rational arithmetic unit based on binary Euclidean algorithm and continued fractions is proposed and designed. The designed low power rational arithmetic unit performs linear rational computation of basic arithmetic operations such as addition, subtraction, multiplication and division on two operands. Redundant binary Euclidean algorithm is used to design the arithmetic unit. Using this on-line algorithm, the parallel nature of the continued fraction arithmetic is exploited to achieve an acceptable performance. Low power performance was the main objective of the design and VLSI implementation of the rational arithmetic unit. The designed low power rational arithmetic unit was modeled in Verilog and synthesized using various TSMC technology libraries for power and area analysis. From three different CMOS fabrication technologies viz. 90nm, 65nm and 40 nm, standard-Vth, Low-Vth and high-Vth cell libraries are considered for synthesis and analysis. A layout of a standalone version of the low power rational arithmetic unit using 0.18 μm TSMC standard library is developed. |
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| Bibliography: | SourceType-Dissertations & Theses-1 ObjectType-Dissertation/Thesis-1 content type line 12 |
| ISBN: | 9781267346551 1267346558 |