A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices

FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vec...

Full description

Saved in:
Bibliographic Details
Published in:International Conference on Field-programmable Logic and Applications pp. 1 - 10
Main Authors: Petura, Oto, Mureddu, Ugo, Bochard, Nathalie, Fischer, Viktor, Bossuet, Lilian
Format: Conference Proceeding
Language:English
Published: EPFL 01.08.2016
Subjects:
Clocks
Cryptography
Entropy
Field programmable gate arrays
Generators
Jitter
Ring oscillators
ISSN:1946-1488
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Abstract FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security's (BSI) recommendations AIS-20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. These results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.
AbstractList FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security's (BSI) recommendations AIS-20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. These results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.
Author Fischer, Viktor
Petura, Oto
Bossuet, Lilian
Bochard, Nathalie
Mureddu, Ugo
Author_xml – sequence: 1
  givenname: Oto
  surname: Petura
  fullname: Petura, Oto
  email: oto.petura@univ-st-etienne.fr
  organization: Hubert Curien Lab., Jean Monnet Univ. St.-EtienneSaint-Etienne, St. Etienne, France
– sequence: 2
  givenname: Ugo
  surname: Mureddu
  fullname: Mureddu, Ugo
  email: ugo.mureddu@univ-st-etienne.fr
  organization: Hubert Curien Lab., Jean Monnet Univ. St.-EtienneSaint-Etienne, St. Etienne, France
– sequence: 3
  givenname: Nathalie
  surname: Bochard
  fullname: Bochard, Nathalie
  email: nathalie.bochard@univ-st-etienne.fr
  organization: Hubert Curien Lab., Jean Monnet Univ. St.-EtienneSaint-Etienne, St. Etienne, France
– sequence: 4
  givenname: Viktor
  surname: Fischer
  fullname: Fischer, Viktor
  email: fischer@univ-st-etienne.fr
  organization: Hubert Curien Lab., Jean Monnet Univ. St.-EtienneSaint-Etienne, St. Etienne, France
– sequence: 5
  givenname: Lilian
  surname: Bossuet
  fullname: Bossuet, Lilian
  email: lilian.bossuet@univ-st-etienne.fr
  organization: Hubert Curien Lab., Jean Monnet Univ. St.-EtienneSaint-Etienne, St. Etienne, France
BookMark eNotj01Lw0AURUdRsNbsBTfzB5LOzJvPZagmFoIWreuSSd5gJE1KEgv99wbs3VwOXA7ce3LT9R0S8shZwjlzq2xbJIJxnRhlDBh3RSJnrLDgHLdSimuy4E7qmEtr70g0jj9sjpLGKr0gzykdf4cTnmkfaLr5jAVbAadVfzi2TdlNdPfxls844DgPm6n0LdLQDzTb5imt8dRUOD6Q21C2I0aXXpKv7GW3fo2L93yzTov4G7iZYgEBfEAMstYMFaLxwXBbVlCC4IZVRjlRMWdBg1fegRcamJRVDUp7WcOSPP17G0TcH4fmUA7n_eU3_AHScEp5
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/FPL.2016.7577379
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9782839918442
2839918447
EISSN 1946-1488
EndPage 10
ExternalDocumentID 7577379
Genre orig-research
GroupedDBID 6IE
6IF
6IL
6IN
AAWTH
ABLEC
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
IEGSK
OCL
RIE
RIL
ID FETCH-LOGICAL-h317t-23f3bfeef4d60e5ee7bf718ac3a32170c7592c098363b5b93b263044cd356b4d3
IEDL.DBID RIE
ISICitedReferencesCount 74
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000386610400081&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 01:40:24 EDT 2025
IsDoiOpenAccess false
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-h317t-23f3bfeef4d60e5ee7bf718ac3a32170c7592c098363b5b93b263044cd356b4d3
OpenAccessLink https://doi.org/10.1109/FPL.2016.7577379
PageCount 10
ParticipantIDs ieee_primary_7577379
PublicationCentury 2000
PublicationDate 2016-08
PublicationDateYYYYMMDD 2016-08-01
PublicationDate_xml – month: 08
  year: 2016
  text: 2016-08
PublicationDecade 2010
PublicationTitle International Conference on Field-programmable Logic and Applications
PublicationTitleAbbrev FPL
PublicationYear 2016
Publisher EPFL
Publisher_xml – name: EPFL
SSID ssj0000547856
Score 1.9384423
Snippet FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Clocks
Cryptography
Entropy
Field programmable gate arrays
Generators
Jitter
Ring oscillators
Title A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices
URI https://ieeexplore.ieee.org/document/7577379
WOSCitedRecordID wos000386610400081&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1JSwMxFA5t8eBJpRV3cvDotOm8rMeiThVKGbRKb2WSeUFBWukG_nszM2VE8OIthIRHXpYvbyfkOjZaZ2j6UQYeIy68i6zBcPEQtOccvCrrp7yO1Hisp1OTNshNHQuDiKXzGXaLZmnLzxduU6jKekooBco0SVMpVcVq1foUViSmErUlkpleko4K1y3Z3U37VT-lhI_k4H-ED0nnJw6PpjXCHJEGztvkbkBXm-UWv-jC08HjcziBPejTyjc88IlOnsZDWmSnXIWBQfS3H0jD15Qm6XBAcyyfhg55Se4ntw_RrhZC9BYQfh3F4MF6RM9zyVAgKusDrGQOMghSBXNKmNgxo0GCFdaAjSUwzl0OQlqewzFpzRdzPCGBkOJaOIbSIvfotcyt19bkfelsjPyUtAsOzD6rdBez3eLP_u4-J_sFkyufuAvSWi83eEn23Hb9vlpelXv0DVgekdM
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3LS8MwGA9zCnpS2cS3OXi0W9u8j0PtNqyl6JTdRpN-QUE22Qv8703bURG8eAsh4SNfHr98b4SuQyVlBirwMmLBo8waTytwFw-ItJQSK8r6Ka-xSBI5Hqu0gW7qWBgAKJ3PoFM0S1t-PjOrQlXWFUwIItQW2maUhkEVrVVrVPwiNRWrbZG-6kZpXDhv8c5m4q8KKiWARPv_I32A2j-ReDitMeYQNWDaQnc9vFjN1_CFZxb3hs_uDHZJgCvvcMcpPHpK-rjIT7lwA53wrz8Au88pjtJ-D-dQPg5t9BLdj24H3qYagvfmMH7phcQSbQEszbkPDEBo64AlMyQjTq7wjWAqNL6ShBPNtCI65MSn1OSEcU1zcoSa09kUjpEjJKhkxgeugVqwkufaSq3ygBsdAj1BrYIDk88q4cVks_jTv7uv0O5g9BhP4mHycIb2CoZXHnLnqLmcr-AC7Zj18n0xvyz36xshaJUa
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=International+Conference+on+Field-programmable+Logic+and+Applications&rft.atitle=A+survey+of+AIS-20%2F31+compliant+TRNG+cores+suitable+for+FPGA+devices&rft.au=Petura%2C+Oto&rft.au=Mureddu%2C+Ugo&rft.au=Bochard%2C+Nathalie&rft.au=Fischer%2C+Viktor&rft.date=2016-08-01&rft.pub=EPFL&rft.eissn=1946-1488&rft.spage=1&rft.epage=10&rft_id=info:doi/10.1109%2FFPL.2016.7577379&rft.externalDocID=7577379