A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices

FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vec...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:International Conference on Field-programmable Logic and Applications s. 1 - 10
Hlavní autori: Petura, Oto, Mureddu, Ugo, Bochard, Nathalie, Fischer, Viktor, Bossuet, Lilian
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: EPFL 01.08.2016
Predmet:
Clocks
Cryptography
Entropy
Field programmable gate arrays
Generators
Jitter
Ring oscillators
ISSN:1946-1488
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security's (BSI) recommendations AIS-20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. These results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.
ISSN:1946-1488
DOI:10.1109/FPL.2016.7577379