Reconciling performance and predictability on a many-core through off-line mapping

We start from a general-purpose many-core architecture designed for average-case performance and ease of use. In particular, its distributed shared memory programming model allows the use of a code generation flow based on the (unmodified) gcc compiler chain. We modify this architecture and extend t...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) S. 1 - 8
Hauptverfasser:	Carle, Thomas, Djemal, Manel, Genius, Daniela, Pecheux, Francois, Potop Butucaru, Dumitru, de Simone, Robert, Wajsburt, Franck, Zhen Zhang
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.05.2014
Schlagworte:	Computer architecture Hardware Processor scheduling Random access memory Real-time systems Scheduling Timing
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!