A Type-Safe Hdl Verified in Coq

Hardware Description Languages (HDL), such as VHDL and Verilog, simplify the circuit specifcation, simulation, and synthesis by enabling different types of abstractions. Hardware verifcation pipelines reduce design faults caused by erroneous transformations of a design specifcation into the layout d...

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Hlavní autor: Tavante, Hanneli Carolina Andreazzi
Médium: Dissertation
Jazyk:angličtina
Vydáno: ProQuest Dissertations & Theses 01.01.2023
Témata:
Behavior
Boolean
C plus plus
Calculus
Circuits
Computer science
Design
Design specifications
Designers
Electrical engineering
Logic
Mathematics
Programming languages
Semantics
Syntax
Temporal logic
Theorems
ISBN:9798379861988
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Shrnutí:Hardware Description Languages (HDL), such as VHDL and Verilog, simplify the circuit specifcation, simulation, and synthesis by enabling different types of abstractions. Hardware verifcation pipelines reduce design faults caused by erroneous transformations of a design specifcation into the layout description. However, there is little work on the language aspect of Verilog itself, and designers tend to trust the language as a source of truth. Unfortunately, unverifed languages may be unreliable and lead to circuit design faults. For instance, in Verilog, values can be converted automatically from one type to another when the context of use requires it, generating undesired bugs due to the automatic conversion.In this thesis, we address the need for a verifed, type-safe language that can rule out undesired faults in hardware projects occasioned by language issues. We present Verifoq,a strongly typed HDL based on a subset of the original Verilog language.Verifoq is developed in the Coq proof assistant, and uses the Simply-Typed Lambda Calculus (STLC) as its core foundation. We develop a fexible small-step operational semantics for our language, and combined with its set of typing rules, we prove that Verifoqis a type-safe language.We also provide several use cases for Verifoq,including a composed verifcation pipeline with Hoare Logic and a multi-staged hardware verifcation pipeline. Finally, we also present possible integration scenarios for High-Level Synthesis applications.
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ISBN:9798379861988