EXPLORING NOVEL DESIGN APPROACH FOR LOW POWER VLSI IN IOT DEVICES
Circuit-level optimization is a critical aspect of designing low-power VLSI circuits for IoT devices. Traditional optimization methods may struggle to explore the vast design space and find the most energy-efficient solutions. This paper introduces a novel approach to circuit-level optimization usin...
Uloženo v:
| Vydáno v: | ICTACT Journal on Microelectronics Ročník 9; číslo 2; s. 1562 - 1567 |
|---|---|
| Hlavní autoři: | , , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
| Vydáno: |
01.07.2023
|
| ISSN: | 2395-1672, 2395-1680 |
| On-line přístup: | Získat plný text |
| Tagy: |
Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
|
| Shrnutí: | Circuit-level optimization is a critical aspect of designing low-power VLSI circuits for IoT devices. Traditional optimization methods may struggle to explore the vast design space and find the most energy-efficient solutions. This paper introduces a novel approach to circuit-level optimization using an evolutionary chaotic algorithm (ECA) in the context of IoT device design. The ECA leverages the principles of chaos theory and evolutionary algorithms to efficiently explore and optimize the design parameters, leading to significant reductions in power consumption while maintaining performance and functionality. The proposed method is evaluated on various IoT circuit designs, demonstrating its effectiveness in achieving enhanced energy efficiency compared to conventional optimization techniques. By harnessing the power of chaos and evolution, this research contributes to the development of sustainable and high-performance IoT devices that can operate on limited power resources. |
|---|---|
| ISSN: | 2395-1672 2395-1680 |
| DOI: | 10.21917/ijme.2023.0272 |