Parallel AES Encryption Engine for Many Core Processor Arrays Using Masked S-Box
With the ever increasing growth of data communication, hardware encryption technology will become an irreplaceable safety technology. In this paper, I present a method of AES encryption and decryption algorithm with 128 bit key on an FPGA. In order to protect “data-at-rest” in memory from differenti...
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| Vydané v: | International journal of recent contributions from engineering, science & IT Ročník 2; číslo 4; s. 35 |
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| Hlavní autori: | , |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
25.10.2014
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| ISSN: | 2197-8581, 2197-8581 |
| On-line prístup: | Získať plný text |
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| Shrnutí: | With the ever increasing growth of data communication, hardware encryption technology will become an irreplaceable safety technology. In this paper, I present a method of AES encryption and decryption algorithm with 128 bit key on an FPGA. In order to protect “data-at-rest” in memory from differential power analysis attacks with high-throughput advanced encryption standard (AES) engine with masked S-Box is proposed. By exploring different granularities of data-level and task-level parallelism, we map 2 implementations of an Advanced Encryption Standard (AES) cipher with online key expansion on a fine-grained many-core system. |
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| ISSN: | 2197-8581 2197-8581 |
| DOI: | 10.3991/ijes.v2i4.4194 |