Error rate reduction of single-qubit gates via noise-aware decomposition into native gates
In the current era of Noisy Intermediate-Scale Quantum (NISQ) technology, the practical use of quantum computers remains inhibited by our inability to aptly decouple qubits from their environment to mitigate computational errors. In this paper, we introduce an approach by which knowledge of a qubit’...
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| Vydané v: | Scientific reports Ročník 12; číslo 1; s. 6379 - 10 |
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| Hlavní autori: | , , , |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
London
Nature Publishing Group UK
16.04.2022
Nature Publishing Group Nature Portfolio |
| Predmet: | |
| ISSN: | 2045-2322, 2045-2322 |
| On-line prístup: | Získať plný text |
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| Shrnutí: | In the current era of Noisy Intermediate-Scale Quantum (NISQ) technology, the practical use of quantum computers remains inhibited by our inability to aptly decouple qubits from their environment to mitigate computational errors. In this paper, we introduce an approach by which knowledge of a qubit’s initial quantum state and the standard parameters describing its decoherence can be leveraged to mitigate the noise present during the execution of a single-qubit gate. We benchmark our protocol using cloud-based access to IBM quantum processors. On ibmq_rome, we demonstrate a reduction of the single-qubit error rate by 38%, from
1.6
×
10
-
3
to
1.0
×
10
-
3
, provided the initial state of the input qubit is known. On ibmq_bogota, we prove that our protocol will never decrease gate fidelity, provided the system’s
T
1
and
T
2
times have not drifted above 100 times their assumed values. The protocol can be used to reduce quantum state preparation errors, as well as to improve the fidelity of quantum circuits for which some knowledge of the qubits’ intermediate states can be inferred. This paper presents a pathway to using information about noise levels and quantum state distributions to significantly reduce error rates associated with quantum gates via optimized decomposition into native hardware gates. |
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| Bibliografia: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 content type line 23 AC02-06CH11357 USDOE |
| ISSN: | 2045-2322 2045-2322 |
| DOI: | 10.1038/s41598-022-10339-0 |