Area-Time-Efficient Secure Comb Scalar Multiplication Architecture Based on Recoding

With the development of mobile communication, digital signatures with low latency, low area, and high security are in increasing demand. Elliptic curve cryptography (ECC) is widely used because of its security and lightweight. Elliptic curve scalar multiplication (ECSM) is the basic arithmetic in EC...

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Veröffentlicht in:Micromachines (Basel) Jg. 15; H. 10; S. 1238
Hauptverfasser: Zhang, Zhantao, Wang, Weijiang, Zhang, Jingqi, He, Xiang, Ma, Mingzhi, Ren, Shiwei, Dang, Hua
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Switzerland MDPI AG 07.10.2024
MDPI
Schlagworte:
Algorithms
Analysis
Computation
Cryptography
Curves
Data encryption
Data security
Digital integrated circuits
Digital signatures
Efficiency
elliptic curve cryptography (ECC)
elliptic curve scalar multiplication (ECSM)
field-programmable gate array (FPGA)
Flexibility
Methods
Multiplication
Number systems
Optimization
prime field (GF)
sample power analysis (SPA)
Security
Germany
prime field (GF)
sample power analysis (SPA)
elliptic curve scalar multiplication (ECSM)
field-programmable gate array (FPGA)
elliptic curve cryptography (ECC)
ISSN:2072-666X, 2072-666X
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Zusammenfassung:With the development of mobile communication, digital signatures with low latency, low area, and high security are in increasing demand. Elliptic curve cryptography (ECC) is widely used because of its security and lightweight. Elliptic curve scalar multiplication (ECSM) is the basic arithmetic in ECC. Based on this background information, we propose our own research objectives. In this paper, a low-latency and low-area ECSM architecture based on the comb algorithm is proposed. The detailed methodology is as follows. The recoding-k algorithm and randomization-Z algorithm are used to improve security, which can resist sample power analysis (SPA) and differential power analysis (DPA). A low-area multi-functional architecture for comb is proposed, which takes into account different stages of the comb algorithm. Based on this, the data dependency is considered and the comb architecture is optimized to achieve a uniform and efficient execution pattern. The interleaved modular multiplication algorithm and modified binary inverse algorithm are used to achieve short clock cycle delay and high frequency while taking into account the need for a low area. The proposed architecture has been implemented on Xilinx Virtex-7 series FPGA to perform ECSM on 256-bits prime field GF(p). In the hardware architecture with only 7351 slices of resource usage, a single ECSM only takes 0.74 ms, resulting in an area-time product (ATP) of 5.41. The implementation results show that our design can compete with the existing state-of-the-art engineering in terms of performance and has higher security. Our design is suitable for computing scenarios where security and computing speed are required. The implementation of the overall architecture is of great significance and inspiration to the research community.
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ISSN:2072-666X
2072-666X
DOI:10.3390/mi15101238