A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power an...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Sensors (Basel, Switzerland) Jg. 23; H. 8; S. 3978
Hauptverfasser: Alimisis, Vassilis, Gennis, Georgios, Gourdouparis, Marios, Dimas, Christos, Sotiriadis, Paul P.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Switzerland MDPI AG 14.04.2023
MDPI
Schlagworte:
Algorithms
analog-hardware implementation
bearing fault application
bulk-controlled circuits
Circuits
Classification
Complementary metal oxide semiconductors
Lagrange multiplier
low-power design
Machine learning
Mathematical models
Neural networks
Ordinary differential equations
Sensors
Signal processing
Simulation methods
Software
support vector machine
Support vector machines
Transistors
analog-hardware implementation
bulk-controlled circuits
support vector machine
low-power design
bearing fault application
ISSN:1424-8220, 1424-8220
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 μW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
content type line 23
ISSN:1424-8220
1424-8220
DOI:10.3390/s23083978