Local Maps of the Polarization and Depolarization in Organic Ferroelectric Field-Effect Transistors
We study the local ferroelectric polarization and depolarization of poly(vinylidene fluoride- co -trifluoroethylene) (P(VDF-TrFE)) in p-type ferroelectric field-effect transistors (FeFETs). Piezoresponse force microscopy (PFM) is used to obtain local maps of the polarization on model metal-semicondu...
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| Published in: | Scientific reports Vol. 6; no. 1; p. 22116 |
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| Main Authors: | , |
| Format: | Journal Article |
| Language: | English |
| Published: |
London
Nature Publishing Group UK
24.02.2016
Nature Publishing Group |
| Subjects: | |
| ISSN: | 2045-2322, 2045-2322 |
| Online Access: | Get full text |
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| Summary: | We study the local ferroelectric polarization and depolarization of poly(vinylidene fluoride-
co
-trifluoroethylene) (P(VDF-TrFE)) in p-type ferroelectric field-effect transistors (FeFETs). Piezoresponse force microscopy (PFM) is used to obtain local maps of the polarization on model metal-semiconductor-ferroelectric stacks and on FeFETs stripped from their top-gate electrode; transfer curves are measured on complete FeFETs. The influence of the semiconductor layer thickness and of the polarity and amplitude of the poling voltage are investigated. In accumulation, the stable “on” state consists of a uniform upward-polarized ferroelectric layer, with compensation holes accumulating at the ferroelectric/semiconducting interface. In depletion, the stable “off” state consists of a depolarized region in the center of the transistor channel, surrounded by partially downward-polarized regions over the source and drain electrodes and neighboring regions. The partial depolarization of these regions is due to the incomplete screening of polarization charges by the charges of the remote electrodes. Therefore, thinner semiconducting layers provide higher downward polarizations, which result in a more depleted transistor channel and a higher charge injection barrier between the electrodes and the semiconductor, leading to lower threshold voltages and higher on/off current values at zero gate bias. Clues for optimization of the devices are finally provided. |
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| Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 content type line 23 |
| ISSN: | 2045-2322 2045-2322 |
| DOI: | 10.1038/srep22116 |