Built-in fast gather control network for efficient support of coherence protocols

Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation-based...

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Veröffentlicht in:	Chronic diseases and translational medicine Jg. 7; H. 2; S. 69 - 80
Hauptverfasser:	Lodde, Mario, Roca, Toni, Flich, José
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Stevenage The Institution of Engineering and Technology 01.03.2013 John Wiley & Sons, Inc
Schlagworte:	built‐in fast gather control network chip multiprocessors Coherence coherence protocol coherence protocols communicating processors Computer simulation Hammer protocol memory controllers memory hierarchy microprocessor chips network control messaging Networks network‐on‐chip NoC on‐chip network Protocol Protocol (computers) protocols Reduction Reproduction shared memory programming model shared memory systems Special Issue: Selected papers from 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC) 2012 tile based design pattern Traffic engineering Traffic flow communicating processors Hammer protocol network-on-chip on-chip network tile based design pattern NoC microprocessor chips memory hierarchy network control messaging memory controllers chip multiprocessors coherence protocols coherence protocol shared memory systems shared memory programming model protocols built-in fast gather control network
ISSN:	1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514
Online-Zugang:	Volltext
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