Built-in fast gather control network for efficient support of coherence protocols

Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation-based...

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Vydáno v:Chronic diseases and translational medicine Ročník 7; číslo 2; s. 69 - 80
Hlavní autoři: Lodde, Mario, Roca, Toni, Flich, José
Médium: Journal Article
Jazyk:angličtina
Vydáno: Stevenage The Institution of Engineering and Technology 01.03.2013
John Wiley & Sons, Inc
Témata:
built‐in fast gather control network
chip multiprocessors
Coherence
coherence protocol
coherence protocols
communicating processors
Computer simulation
Hammer protocol
memory controllers
memory hierarchy
microprocessor chips
network control messaging
Networks
network‐on‐chip
NoC
on‐chip network
Protocol
Protocol (computers)
protocols
Reduction
Reproduction
shared memory programming model
shared memory systems
Special Issue: Selected papers from 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC) 2012
tile based design pattern
Traffic engineering
Traffic flow
communicating processors
Hammer protocol
network-on-chip
on-chip network
tile based design pattern
NoC
microprocessor chips
memory hierarchy
network control messaging
memory controllers
chip multiprocessors
coherence protocols
coherence protocol
shared memory systems
shared memory programming model
protocols
built-in fast gather control network
ISSN:1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514
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Shrnutí:Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation-based protocol is used, where shared copies are invalidated before a write operation. In this study, the authors propose a NoC re-organisation in which a small and fast dedicated control network is used to transmit acknowledgement messages related to the invalidation process, thus relieving the NoC from a considerable percentage of traffic. The dedicated control network is evaluated both with full map directories and with a broadcast-based protocol (Hammer). Experimental evaluation shows significant gains in performance. With a low area overhead (<2.5%), the control network reduces NoC traffic and miss latency, thus reducing execution time up to 16%. Simulation results show a reduction of network traffic up to 80% and a reduction of store and load miss latency up to 70 and 40%, respectively.
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ISSN:1751-8601
1751-861X
2095-882X
1751-861X
2589-0514
DOI:10.1049/iet-cdt.2012.0056