Built-in fast gather control network for efficient support of coherence protocols
Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation-based...
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| Veröffentlicht in: | Chronic diseases and translational medicine Jg. 7; H. 2; S. 69 - 80 |
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| Format: | Journal Article |
| Sprache: | Englisch |
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Stevenage
The Institution of Engineering and Technology
01.03.2013
John Wiley & Sons, Inc |
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| ISSN: | 1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514 |
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| Abstract | Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation-based protocol is used, where shared copies are invalidated before a write operation. In this study, the authors propose a NoC re-organisation in which a small and fast dedicated control network is used to transmit acknowledgement messages related to the invalidation process, thus relieving the NoC from a considerable percentage of traffic. The dedicated control network is evaluated both with full map directories and with a broadcast-based protocol (Hammer). Experimental evaluation shows significant gains in performance. With a low area overhead (<2.5%), the control network reduces NoC traffic and miss latency, thus reducing execution time up to 16%. Simulation results show a reduction of network traffic up to 80% and a reduction of store and load miss latency up to 70 and 40%, respectively. |
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| AbstractList | Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually, an invalidation-based protocol is used, where shared copies are invalidated before a write operation. In this study, the authors propose a NoC re-organisation in which a small and fast dedicated control network is used to transmit acknowledgement messages related to the invalidation process, thus relieving the NoC from a considerable percentage of traffic. The dedicated control network is evaluated both with full map directories and with a broadcast-based protocol (Hammer). The experimental evaluation shows significant gains in performance. With a low area overhead (<2.5%), the control network reduces NoC traffic and miss latency, thus reducing execution time up to 16%. The simulation results show a reduction of network traffic up to 80% and a reduction of store and load miss latency up to 70% and 40%, respectively. Future chip multiprocessors will include hundreds of cores organised in a tile‐based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation‐based protocol is used, where shared copies are invalidated before a write operation. In this study, the authors propose a NoC re‐organisation in which a small and fast dedicated control network is used to transmit acknowledgement messages related to the invalidation process, thus relieving the NoC from a considerable percentage of traffic. The dedicated control network is evaluated both with full map directories and with a broadcast‐based protocol (Hammer). Experimental evaluation shows significant gains in performance. With a low area overhead (<2.5%), the control network reduces NoC traffic and miss latency, thus reducing execution time up to 16%. Simulation results show a reduction of network traffic up to 80% and a reduction of store and load miss latency up to 70 and 40%, respectively. |
| Author | Flich, José Roca, Toni Lodde, Mario |
| Author_xml | – sequence: 1 givenname: Mario surname: Lodde fullname: Lodde, Mario email: mlodde@gap.upv.es organization: Parallel Architectures Group, DISCA, Universitat Politècnica de València, Spain – sequence: 2 givenname: Toni surname: Roca fullname: Roca, Toni organization: Parallel Architectures Group, DISCA, Universitat Politècnica de València, Spain – sequence: 3 givenname: José surname: Flich fullname: Flich, José organization: Parallel Architectures Group, DISCA, Universitat Politècnica de València, Spain |
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| Cites_doi | 10.1201/b10477 10.1145/1669112.1669143 10.1145/2155620.2155630 10.1109/HPCA.2011.5749723 10.1109/TC.2009.129 10.1109/MM.2007.43 10.1145/1150019.1136515 10.1109/MICRO.2008.4771805 10.1109/L-CA.2008.11 10.1145/1080695.1069991 10.1109/ISCA.2005.42 10.1109/MICRO.2006.27 10.2200/S00346ED1V01Y201104CAC016 10.1109/HPCA.2010.5416635 10.1109/NOCS.2007.42 10.1109/MM.2010.31 10.1109/HPCA.2001.903254 10.1109/HPCA.2008.4658623 10.1145/581199.581253 10.1007/978-3-642-21878-1_12 |
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| Keywords | communicating processors Hammer protocol network-on-chip on-chip network tile based design pattern NoC microprocessor chips memory hierarchy network control messaging memory controllers chip multiprocessors coherence protocols coherence protocol shared memory systems shared memory programming model protocols built-in fast gather control network |
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| Snippet | Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming... Future chip multiprocessors will include hundreds of cores organised in a tile‐based design pattern. These systems commonly employ a shared memory programming... |
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| SubjectTerms | built‐in fast gather control network chip multiprocessors Coherence coherence protocol coherence protocols communicating processors Computer simulation Hammer protocol memory controllers memory hierarchy microprocessor chips network control messaging Networks network‐on‐chip NoC on‐chip network Protocol Protocol (computers) protocols Reduction Reproduction shared memory programming model shared memory systems Special Issue: Selected papers from 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC) 2012 tile based design pattern Traffic engineering Traffic flow |
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