Improving latency tolerance of multithreading through decoupling

The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, designed over a superscalar core, are therefore directly concerned by this problem...

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Veröffentlicht in:	IEEE transactions on computers Jg. 50; H. 10; S. 1084 - 1094
Hauptverfasser:	Parcerisa, J.-M., Gonzalez, A.
Format:	Journal Article Verlag
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.10.2001 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Access/execute decoupling Architecture Arquitectura de computadors Complexity Critical path Decoupling Delay effects Dynamic scheduling Dynamical systems Dynamics Hardware Hardware complexity Informàtica Instruction-level parallelism Latency hiding Microarchitecture Multithreading Out of order Parallel processing (Electronic computers) Process design Processament en paral·lel (Ordinadors) Processor scheduling Processors Scalability Simultaneous multithreading processors Surface-mount technology Tolerances Àrees temàtiques de la UPC
ISSN:	0018-9340, 1557-9956
Online-Zugang:	Volltext
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