Improving latency tolerance of multithreading through decoupling

The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, designed over a superscalar core, are therefore directly concerned by this problem...

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Veröffentlicht in:IEEE transactions on computers Jg. 50; H. 10; S. 1084 - 1094
Hauptverfasser: Parcerisa, J.-M., Gonzalez, A.
Format: Journal Article Verlag
Sprache:Englisch
Veröffentlicht: New York IEEE 01.10.2001
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Access/execute decoupling
Architecture
Arquitectura de computadors
Complexity
Critical path
Decoupling
Delay effects
Dynamic scheduling
Dynamical systems
Dynamics
Hardware
Hardware complexity
Informàtica
Instruction-level parallelism
Latency hiding
Microarchitecture
Multithreading
Out of order
Parallel processing (Electronic computers)
Process design
Processament en paral·lel (Ordinadors)
Processor scheduling
Processors
Scalability
Simultaneous multithreading processors
Surface-mount technology
Tolerances
Àrees temàtiques de la UPC
ISSN:0018-9340, 1557-9956
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Zusammenfassung:The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, designed over a superscalar core, are therefore directly concerned by this problem. The article presents and evaluates a novel processor microarchitecture which combines two paradigms: simultaneous multithreading and access/execute decoupling. Since its decoupled units issue instructions in order, this architecture is significantly less complex, in terms of critical path delays, than a centralized out-of-order design, and it is more effective for future growth in issue-width and clock speed. We investigate how both techniques complement each other. Since decoupling features an excellent memory latency hiding efficiency, the large amount of parallelism exploited by multithreading may be used to hide the latency of functional units and keep them fully utilized. The study shows that, by adding decoupling to a multithreaded architecture, fewer threads are needed to achieve maximum throughput. Therefore, in addition to the obvious hardware complexity reduction, it places lower demands on the memory system. The study also reveals that multithreading by itself exhibits little memory latency tolerance. Results suggest that most of the latency hiding effectiveness of SMT architectures comes from the dynamic scheduling. On the other hand, decoupling is very effective at hiding memory latency. An increase in the cache miss penalty from 1 to 32 cycles reduces the performance of a 4-context multithreaded decoupled processor by less than 2 percent. For the nondecoupled multithreaded processor, the loss of performance is about 23 percent.
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ISSN:0018-9340
1557-9956
DOI:10.1109/12.956093