IP core implementation of a self-organizing neural network

This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a...

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Bibliographic Details

Published in:	IEEE transactions on neural networks Vol. 14; no. 5; pp. 1085 - 1096
Main Authors:	Hendry, D.C., Duncan, A.A., Lightowler, N.
Format:	Journal Article
Language:	English
Published:	United States IEEE 01.09.2003
Subjects:	Artificial neural networks Costs Delay Field programmable gate arrays Hardware Intellectual property Neural networks Neurons Power dissipation Silicon
ISSN:	1045-9227
Online Access:	Get full text
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