IP core implementation of a self-organizing neural network

This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a...

Celý popis

Podrobná bibliografia

Vydané v:	IEEE transactions on neural networks Ročník 14; číslo 5; s. 1085 - 1096
Hlavní autori:	Hendry, D.C., Duncan, A.A., Lightowler, N.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	United States IEEE 01.09.2003
Predmet:	Artificial neural networks Costs Delay Field programmable gate arrays Hardware Intellectual property Neural networks Neurons Power dissipation Silicon
ISSN:	1045-9227
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!