IP core implementation of a self-organizing neural network

This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a...

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Vydané v:IEEE transactions on neural networks Ročník 14; číslo 5; s. 1085 - 1096
Hlavní autori: Hendry, D.C., Duncan, A.A., Lightowler, N.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: United States IEEE 01.09.2003
Predmet:
Artificial neural networks
Costs
Delay
Field programmable gate arrays
Hardware
Intellectual property
Neural networks
Neurons
Power dissipation
Silicon
ISSN:1045-9227
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Shrnutí:This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a 16 element reference vector. Migrating the design to a soft IP core presents challenges in achieving the required performance as regards area, power, and clock speed. This same migration, however, offers opportunities for parameterizing the design in a manner which permits a single soft core to meet the requirements of many end users. Thus, the number of neurons within the single instruction multiple data (SIMD) array, the number of elements per reference vector, and the number of bits of each such element are defined by synthesis time parameters. The construction of the SIMD array of neurons is presented including performance results as regards power, area, and classifications per second . For typical parameters (256 neurons with 16 elements per reference vector) the design provides over 2 000 000 classifications per second using a mainstream 0.18-/spl mu/m digital process. A RISC processor, the array controller (AC), provides both the instruction stream and data to the SIMD array of neurons and an interface to a host processor. The design of this processor is discussed with emphasis on the control aspects which permit supply of a continuous instruction stream to the SIMD array and a flexible interface with the host processor.
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ISSN:1045-9227
DOI:10.1109/TNN.2003.816353