A fully-mapped and energy-efficient FPGA accelerator for dual-function AI-based analysis of ECG

In this paper, a fully-mapped field programmable gate array (FPGA) accelerator is proposed for artificial intelligence (AI)-based analysis of electrocardiogram (ECG). It consists of a fully-mapped 1-D convolutional neural network (CNN) and a fully-mapped heart rate estimator, which constitute a comp...

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Bibliographic Details
Published in:Frontiers in physiology Vol. 14; p. 1079503
Main Authors: Liu, Wenhan, Guo, Qianxi, Chen, Siyun, Chang, Sheng, Wang, Hao, He, Jin, Huang, Qijun
Format: Journal Article
Language:English
Published: Switzerland Frontiers Media S.A 06.02.2023
Subjects:
artificial intelligence (AI)
convolutional neural network (CNN)
electrocardiagram (ECG)
field programmable gate array (FPGA)
Physiology
signal processing
field programmable gate array (FPGA)
convolutional neural network (CNN)
signal processing
electrocardiagram (ECG)
artificial intelligence (AI)
ISSN:1664-042X, 1664-042X
Online Access:Get full text
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Summary:In this paper, a fully-mapped field programmable gate array (FPGA) accelerator is proposed for artificial intelligence (AI)-based analysis of electrocardiogram (ECG). It consists of a fully-mapped 1-D convolutional neural network (CNN) and a fully-mapped heart rate estimator, which constitute a complementary dual-function analysis. The fully-mapped design projects each layer of the 1-D CNN to a hardware module on an Intel Cyclone V FPGA, and a virtual flatten layer is proposed to effectively bridge the feature extraction layers and fully-connected layer. Also, the fully-mapped design maximizes computational parallelism to accelerate CNN inference. For the fully-mapped heart rate estimator, it performs pipelined transformations, self-adaptive threshold calculation, and heartbeat count on the FPGA, without multiplexed usage of hardware resources. Furthermore, heart rate calculation is elaborately analyzed and optimized to remove division and acceleration, resulting in an efficient method suitable for hardware implementation. According to our experiments on 1-D CNN, the accelerator can achieve 43.08× and 8.38× speedup compared with the software implementations on ARM-Cortex A53 quad-core processor and Intel Core i7-8700 CPU, respectively. For the heart rate estimator, the hardware implementations are 25.48× and 1.55× faster than the software implementations on the two aforementioned platforms. Surprisingly, the accelerator achieves an energy efficiency of 63.48 GOPS/W, which obviously surpasses existing studies. Considering its power consumption is only 67.74 mW, it may be more suitable for resource-limited applications, such as wearable and portable devices for ECG monitoring.
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Edited by: Muhammad Usman, Chosun University, Republic of Korea
Reviewed by: Muhammad Sohail Ibrahim, Zhejiang University, China
Nalesh S., Cochin University of Science and Technology, India
This article was submitted to Computational Physiology and Medicine, a section of the journal Frontiers in Physiology
ISSN:1664-042X
1664-042X
DOI:10.3389/fphys.2023.1079503