A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation

A domain specific multicore processor for public-key cryptography is proposed in this paper. This processor provides flexible and efficient computation for various forms of RSA and ECC algorithms, fulfilling low-latency or high-throughput requirements of different application scenarios. By using a h...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Jg. 62; H. 5; S. 1372 - 1381
Hauptverfasser: Han, Jun, Dou, Renfeng, Zeng, Lingyun, Wang, Shuai, Yu, Zhiyi, Zeng, Xiaoyang
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.05.2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithms
Architecture (computers)
Circuits
Computational efficiency
Cryptography
Data encryption
ECC
Hardware
Microprocessors
Modular
modular multiplication
multicore
Multicore processing
Public key
Reduction
Registers
RSA
Software algorithms
ISSN:1549-8328, 1558-0806
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Zusammenfassung:A domain specific multicore processor for public-key cryptography is proposed in this paper. This processor provides flexible and efficient computation for various forms of RSA and ECC algorithms, fulfilling low-latency or high-throughput requirements of different application scenarios. By using a heterogeneous multicore architecture, the proposed processor enables high speed parallel implementations of kernel arithmetics of public-key algorithms. A long-word-length modular multiplication can be partitioned into parallel tasks executed by the high performance multipliers distributed in multiple cores. Some dedicated communication mechanisms minimize inter-core data transferring latencies of the processor. The proposed processor is implemented under TSMC 65 nm LP CMOS technology. Experimental results show that our design outperforms previous works based on varied platforms in performance, for instance, it can complete a 1024-bit RSA encryption in 0.087 ms at 960 MHz. Moreover, we also study the area reduction techniques for proposed multicore processor from the perspectives of algorithm, architecture, and circuit.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2015.2407431