Synergistic Dynamical Decoupling and Circuit Design for Enhanced Algorithm Performance on Near-Term Quantum Devices
Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit d...
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01.07.2024
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| Abstract | Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms. |
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| AbstractList | Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms. Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms.Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms. |
| Audience | Academic |
| Author | Polian, Ilia Ji, Yanjun |
| Author_xml | – sequence: 1 givenname: Yanjun orcidid: 0000-0002-9129-9268 surname: Ji fullname: Ji, Yanjun – sequence: 2 givenname: Ilia orcidid: 0000-0002-6563-2725 surname: Polian fullname: Polian, Ilia |
| BackLink | https://www.ncbi.nlm.nih.gov/pubmed/39056948$$D View this record in MEDLINE/PubMed |
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| Cites_doi | 10.1088/2058-9565/ab8e92 10.1038/ncomms5213 10.36227/techrxiv.21786146 10.1109/TQE.2020.3030314 10.1103/PhysRevLett.119.180509 10.1145/3466752.3480059 10.1103/PhysRevA.79.062324 10.1103/PhysRevLett.132.010601 10.1103/PhysRev.94.630 10.1126/science.1192739 10.1103/PhysRevLett.82.2417 10.1038/nphys1994 10.1007/s11128-022-03766-5 10.1103/PhysRevB.92.060301 10.1103/RevModPhys.88.041001 10.1103/PhysRevA.108.022610 10.1103/PhysRevLett.106.240501 10.1088/2058-9565/abae7d 10.1103/PhysRevLett.131.210802 10.1007/s11433-022-2057-y 10.1103/PhysRevLett.98.100504 10.1103/PhysRevApplied.20.064027 10.1038/s41567-020-01105-y 10.1038/s42254-021-00348-9 10.1103/PhysRevA.85.052324 10.1103/PhysRevLett.121.220502 10.1109/TQE.2022.3203153 10.1038/nature08470 10.1103/PhysRevLett.108.086802 10.1117/12.2227479 10.1063/1.1716296 10.1103/PhysRevLett.127.030501 10.1098/rsta.2011.0355 10.1109/QCE53715.2022.00040 10.1016/j.physrep.2024.03.002 10.1103/PhysRevA.85.032306 10.1016/j.physrep.2022.08.003 10.1103/PRXQuantum.4.030335 10.1103/PhysRevA.87.042309 10.1103/PhysRevApplied.16.054047 10.1109/MICRO50266.2020.00027 10.1103/PhysRevLett.92.177902 10.1103/PhysRevApplied.18.024068 10.1109/ISCA59077.2024.00031 10.1103/RevModPhys.95.045005 10.22331/q-2018-08-06-79 |
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| SubjectTerms | Algorithms Analysis Approximation Circuit design Circuits Computer industry Decoupling Design analysis Design factors Design optimization Devices dynamical decoupling Effectiveness Error analysis Hardware Impact analysis Investment analysis near-term quantum devices Optimization techniques quantum circuit design quantum error mitigation Software Success Synergistic effect |
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| Title | Synergistic Dynamical Decoupling and Circuit Design for Enhanced Algorithm Performance on Near-Term Quantum Devices |
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