A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation

We present an automated bit-width optimization methodology for polynomial-based hardware function evaluation. Due to the analytical nature of the approach, overflow protection and precision accurate to one unit in the last place (ulp) can be guaranteed. A range analysis technique based on computing...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:IEEE transactions on computers Ročník 56; číslo 4; s. 567 - 571
Hlavní autoři: Lee, Dong-U, Villasenor, John D.
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.04.2007
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Computation
Computer arithmetic
Derivatives
elementary function approximation
Estimation
field programmable gate arrays
finite wordlength effects
Hardware
Indexes
Mathematical analysis
Mathematical models
Methodology
minimax approximation and algorithms
Optimization
Quantization (signal)
Resource management
Simulated annealing
ISSN:0018-9340, 1557-9956
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:We present an automated bit-width optimization methodology for polynomial-based hardware function evaluation. Due to the analytical nature of the approach, overflow protection and precision accurate to one unit in the last place (ulp) can be guaranteed. A range analysis technique based on computing the root of the derivative of a signal is utilized to determine the minimal number of integer bits. Fractional bit requirements are established using an analytical error expression derived from the functions that occur along the data path. Global fractional bit optimization across multiple computation stages is performed using simulated annealing and circuit area estimation functions
Bibliografie:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 14
content type line 23
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2007.1013