Novel digital NGD Methodology for FPGA-based Embedded Systems

Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the v...

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Vydané v:IEEE access Ročník 12; s. 1
Hlavní autori: Randriatsiferana, Rivo, Lorandel, Jordane, Salvador, Ruben, Moy, Christophe
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Piscataway IEEE 01.01.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Abstract Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems.
AbstractList Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. NGD time-domain characterization was conducted using a sampling frequency of 1 MHz and Gaussian and sinc input signal waveforms. The calculated and experimental results are in excellent agreement, showing a desired time advance of 6 μ s and an average cross-correlation of 98%. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems.
Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. NGD time-domain characterization was conducted using a sampling frequency of 1 MHz and Gaussian and sinc input signal waveforms. The calculated and experimental results are in excellent agreement, showing a desired time advance of [Formula Omitted]s and an average cross-correlation of 98%. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems.
Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems.
Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. NGD time-domain characterization was conducted using a sampling frequency of 1 MHz and Gaussian and sinc input signal waveforms. The calculated and experimental results are in excellent agreement, showing a desired time advance of <tex-math notation="LaTeX">$6~\mu $ </tex-math>s and an average cross-correlation of 98%. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems.
Author Salvador, Ruben
Moy, Christophe
Randriatsiferana, Rivo
Lorandel, Jordane
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10.1109/MMM.2020.3035862
10.1109/TCSI.2014.2361035
10.1080/03091902.2021.1967490
10.1016/j.vlsi.2023.02.005
10.1109/TVT.2020.3018817
10.1007/s11265-020-01575-6
10.1109/HST.2017.7951829
10.1587/elex.16.20190010
10.1109/LMWC.2017.2711572
10.1007/s10470-021-01826-x
10.1109/MCOM.011.2000863
10.1016/j.physleta.2019.07.015
10.12720/ijsps.2.2.132-138
10.1109/ACCESS.2022.3226514
10.1103/PhysRevE.103.L020401
10.5539/apr.v3n2p81
10.1119/1.18813
10.1109/MWSCAS.2009.5236044
10.1109/JSTQE.2002.807979
10.1109/TCAD.2021.3136982
10.1109/TCSII.2020.3012869
10.1109/TCSI.2015.2395631
10.1002/cta.1902
10.1063/1.5052497
10.2528/PIERC22011705
10.1109/TIE.2023.3321988
10.1109/TCSI.2021.3055416
10.1109/TIE.2022.3213904
10.1016/j.jestch.2023.101590
10.1080/03091902.2020.1799097
10.1016/S0375-9601(97)00244-2
10.1109/JSEN.2023.3342219
10.1109/TPEL.2017.2691062
10.1103/PhysRevApplied.9.034011
10.1016/B978-0-12-386914-2.00015-7
10.1109/TCSII.2014.2387615
10.1109/TCSII.2023.3276389
10.1080/00207721.2018.1443232
10.1109/TCSII.2014.2335437
10.1109/TIE.2021.3109543
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Keywords Time-frequency analysis
Finite impulse response filters
Cutoff frequency
Circuits
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Delays
Field programmable gate arrays
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References ref13
ref35
ref12
ref34
ref15
ref37
ref14
ref36
ref31
ref30
ref11
ref33
ref10
ref32
ref2
ref1
ref17
ref39
(ref44) 2016
ref16
ref38
ref19
ref18
ref24
ref23
ref26
ref25
ref20
ref42
ref41
ref22
ref21
ref28
ref27
ref29
ref8
ref7
ref9
ref3
ref6
ref5
Lei (ref4) 2012; 6
ref40
(ref43) 2020
References_xml – ident: ref39
  doi: 10.1038/s41598-020-74351-y
– ident: ref36
  doi: 10.1109/MMM.2020.3035862
– volume-title: PMODDA2T Reference Manual
  year: 2016
  ident: ref44
– ident: ref9
  doi: 10.1109/TCSI.2014.2361035
– ident: ref38
  doi: 10.1080/03091902.2021.1967490
– ident: ref14
  doi: 10.1016/j.vlsi.2023.02.005
– ident: ref6
  doi: 10.1109/TVT.2020.3018817
– ident: ref42
  doi: 10.1007/s11265-020-01575-6
– ident: ref5
  doi: 10.1109/HST.2017.7951829
– ident: ref22
  doi: 10.1587/elex.16.20190010
– ident: ref20
  doi: 10.1109/LMWC.2017.2711572
– ident: ref25
  doi: 10.1007/s10470-021-01826-x
– ident: ref3
  doi: 10.1109/MCOM.011.2000863
– ident: ref27
  doi: 10.1016/j.physleta.2019.07.015
– ident: ref28
  doi: 10.12720/ijsps.2.2.132-138
– ident: ref32
  doi: 10.1109/ACCESS.2022.3226514
– ident: ref31
  doi: 10.1103/PhysRevE.103.L020401
– ident: ref13
  doi: 10.5539/apr.v3n2p81
– ident: ref15
  doi: 10.1119/1.18813
– volume: 6
  start-page: 1037
  issue: 3
  year: 2012
  ident: ref4
  article-title: Effect of group delay on channel estimation performance in OFDM system
  publication-title: Appl. Math. Inf. Sci.
– ident: ref7
  doi: 10.1109/MWSCAS.2009.5236044
– ident: ref17
  doi: 10.1109/JSTQE.2002.807979
– ident: ref23
  doi: 10.1109/TCAD.2021.3136982
– ident: ref40
  doi: 10.1109/TCSII.2020.3012869
– ident: ref10
  doi: 10.1109/TCSI.2015.2395631
– ident: ref18
  doi: 10.1002/cta.1902
– ident: ref19
  doi: 10.1063/1.5052497
– ident: ref26
  doi: 10.2528/PIERC22011705
– ident: ref35
  doi: 10.1109/TIE.2023.3321988
– ident: ref21
  doi: 10.1109/TCSI.2021.3055416
– ident: ref30
  doi: 10.1109/TIE.2022.3213904
– volume-title: 7 Series FPGAS and ZYNQ-7000 All Programmable Soc XADC Dual 12-bit 1-MSPS Analogto-Digital Converter User Guide (UG480)
  year: 2020
  ident: ref43
– ident: ref24
  doi: 10.1016/j.jestch.2023.101590
– ident: ref37
  doi: 10.1080/03091902.2020.1799097
– ident: ref16
  doi: 10.1016/S0375-9601(97)00244-2
– ident: ref34
  doi: 10.1109/JSEN.2023.3342219
– ident: ref11
  doi: 10.1109/TPEL.2017.2691062
– ident: ref2
  doi: 10.1103/PhysRevApplied.9.034011
– ident: ref41
  doi: 10.1016/B978-0-12-386914-2.00015-7
– ident: ref1
  doi: 10.1109/TCSII.2014.2387615
– ident: ref33
  doi: 10.1109/TCSII.2023.3276389
– ident: ref12
  doi: 10.1080/00207721.2018.1443232
– ident: ref8
  doi: 10.1109/TCSII.2014.2335437
– ident: ref29
  doi: 10.1109/TIE.2021.3109543
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Snippet Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a...
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SubjectTerms Circuits
Cross correlation
Cutoff frequency
Delays
Digital NGD design
Digital signal processing
Embedded systems
Engineering Sciences
Field programmable gate arrays
Finite impulse response filters
FIR filters
FIR-Based NGD
Group delay
Methodology
NGD FPGA
NGD implementation
Signal Processing
Time domain analysis
Time-frequency analysis
Waveforms
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Title Novel digital NGD Methodology for FPGA-based Embedded Systems
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