Novel digital NGD Methodology for FPGA-based Embedded Systems
Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the v...
Uložené v:
| Vydané v: | IEEE access Ročník 12; s. 1 |
|---|---|
| Hlavní autori: | , , , |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
Piscataway
IEEE
01.01.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Predmet: | |
| ISSN: | 2169-3536, 2169-3536 |
| On-line prístup: | Získať plný text |
| Tagy: |
Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
|
| Abstract | Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems. |
|---|---|
| AbstractList | Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. NGD time-domain characterization was conducted using a sampling frequency of 1 MHz and Gaussian and sinc input signal waveforms. The calculated and experimental results are in excellent agreement, showing a desired time advance of 6 μ s and an average cross-correlation of 98%. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems. Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. NGD time-domain characterization was conducted using a sampling frequency of 1 MHz and Gaussian and sinc input signal waveforms. The calculated and experimental results are in excellent agreement, showing a desired time advance of [Formula Omitted]s and an average cross-correlation of 98%. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems. Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems. Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. NGD time-domain characterization was conducted using a sampling frequency of 1 MHz and Gaussian and sinc input signal waveforms. The calculated and experimental results are in excellent agreement, showing a desired time advance of <tex-math notation="LaTeX">$6~\mu $ </tex-math>s and an average cross-correlation of 98%. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems. |
| Author | Salvador, Ruben Moy, Christophe Randriatsiferana, Rivo Lorandel, Jordane |
| Author_xml | – sequence: 1 givenname: Rivo orcidid: 0000-0001-8630-2971 surname: Randriatsiferana fullname: Randriatsiferana, Rivo organization: Univ Rennes, CNRS, IETR-UMR 6164, Rennes, France – sequence: 2 givenname: Jordane surname: Lorandel fullname: Lorandel, Jordane organization: Univ Rennes, CNRS, IETR-UMR 6164, Rennes, France – sequence: 3 givenname: Ruben orcidid: 0000-0002-0021-5808 surname: Salvador fullname: Salvador, Ruben organization: CentraleSupélec, Inria, Univ Rennes, CNRS, IRISA, France – sequence: 4 givenname: Christophe surname: Moy fullname: Moy, Christophe organization: Univ Rennes, CNRS, IETR-UMR 6164, Rennes, France |
| BackLink | https://hal.science/hal-04596488$$DView record in HAL |
| BookMark | eNqFkc1qGzEUhUVJoWmaJ2gXA111Ma6kqx9r0YVxHSfgJgG3a6HR1ThjxlYqTQJ--8qZENJuqo0uh3O-i3Tek5N93AdCPjI6YYyar7P5fLFeTzjlYgKCAgV4Q045U6YGCerk1fyOnOe8peVMiyT1Kfl2HR9DX2G36QbXV9fL79WPMNxFjH3cHKo2puridjmrG5cDVotdExDLsD7kIezyB_K2dX0O58_3Gfl1sfg5v6xXN8ur-WxVeyFgqLVQSoBj3GBQATVrKCgnJBoDHr3QGpRpPVWN0BKQc0RkBnkrBGeN8HBGrkYuRre196nbuXSw0XX2SYhpY10aOt8H67xALlQIoJnAwBrZSINgUAlDvdSF9WVk3bn-L9TlbGWPGhXSKDGdPrLi_Tx671P8_RDyYLfxIe3LUy1QaSTTXB-JMLp8ijmn0L5gGbXHiuxYkT1WZJ8rKinzT8qXCoYu7ofkuv4_2U9jtgshvNomofwlhz-aZpz1 |
| CODEN | IAECCG |
| CitedBy_id | crossref_primary_10_1016_j_aeue_2024_155596 |
| Cites_doi | 10.1038/s41598-020-74351-y 10.1109/MMM.2020.3035862 10.1109/TCSI.2014.2361035 10.1080/03091902.2021.1967490 10.1016/j.vlsi.2023.02.005 10.1109/TVT.2020.3018817 10.1007/s11265-020-01575-6 10.1109/HST.2017.7951829 10.1587/elex.16.20190010 10.1109/LMWC.2017.2711572 10.1007/s10470-021-01826-x 10.1109/MCOM.011.2000863 10.1016/j.physleta.2019.07.015 10.12720/ijsps.2.2.132-138 10.1109/ACCESS.2022.3226514 10.1103/PhysRevE.103.L020401 10.5539/apr.v3n2p81 10.1119/1.18813 10.1109/MWSCAS.2009.5236044 10.1109/JSTQE.2002.807979 10.1109/TCAD.2021.3136982 10.1109/TCSII.2020.3012869 10.1109/TCSI.2015.2395631 10.1002/cta.1902 10.1063/1.5052497 10.2528/PIERC22011705 10.1109/TIE.2023.3321988 10.1109/TCSI.2021.3055416 10.1109/TIE.2022.3213904 10.1016/j.jestch.2023.101590 10.1080/03091902.2020.1799097 10.1016/S0375-9601(97)00244-2 10.1109/JSEN.2023.3342219 10.1109/TPEL.2017.2691062 10.1103/PhysRevApplied.9.034011 10.1016/B978-0-12-386914-2.00015-7 10.1109/TCSII.2014.2387615 10.1109/TCSII.2023.3276389 10.1080/00207721.2018.1443232 10.1109/TCSII.2014.2335437 10.1109/TIE.2021.3109543 |
| ContentType | Journal Article |
| Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024 Attribution |
| Copyright_xml | – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024 – notice: Attribution |
| DBID | 97E ESBDL RIA RIE AAYXX CITATION 7SC 7SP 7SR 8BQ 8FD JG9 JQ2 L7M L~C L~D 1XC VOOES DOA |
| DOI | 10.1109/ACCESS.2024.3403033 |
| DatabaseName | IEEE All-Society Periodicals Package (ASPP) 2005–Present IEEE Xplore Open Access Journals IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Engineered Materials Abstracts METADEX Technology Research Database Materials Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional Hyper Article en Ligne (HAL) Hyper Article en Ligne (HAL) (Open Access) DOAJ Open Access Full Text |
| DatabaseTitle | CrossRef Materials Research Database Engineered Materials Abstracts Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Advanced Technologies Database with Aerospace METADEX Computer and Information Systems Abstracts Professional |
| DatabaseTitleList | Materials Research Database |
| Database_xml | – sequence: 1 dbid: DOA name: DOAJ Open Access Full Text url: https://www.doaj.org/ sourceTypes: Open Website – sequence: 2 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISSN | 2169-3536 |
| EndPage | 1 |
| ExternalDocumentID | oai_doaj_org_article_ac4d246ee3714de1b5b59d39d6490c57 oai:HAL:hal-04596488v1 10_1109_ACCESS_2024_3403033 10534772 |
| Genre | orig-research |
| GroupedDBID | 0R~ 5VS 6IK 97E AAJGR ABAZT ABVLG ACGFS ADBBV ALMA_UNASSIGNED_HOLDINGS BCNDV BEFXN BFFAM BGNUA BKEBE BPEOZ EBS ESBDL GROUPED_DOAJ IPLJI JAVBF KQ8 M43 M~E O9- OCL OK1 RIA RIE RNS 4.4 AAYXX AGSQL CITATION EJD 7SC 7SP 7SR 8BQ 8FD JG9 JQ2 L7M L~C L~D 1XC VOOES |
| ID | FETCH-LOGICAL-c443t-746643a129de6ed71b036a45d993cdc477369fc06b4753d22ddd19d2f4421b4c3 |
| IEDL.DBID | DOA |
| ISICitedReferencesCount | 1 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001231420400001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 2169-3536 |
| IngestDate | Fri Oct 03 12:43:20 EDT 2025 Tue Nov 04 06:22:34 EST 2025 Sun Jun 29 15:54:14 EDT 2025 Sat Nov 29 06:25:44 EST 2025 Tue Nov 18 21:48:02 EST 2025 Wed Aug 27 02:05:25 EDT 2025 |
| IsDoiOpenAccess | true |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Keywords | Time-frequency analysis Finite impulse response filters Cutoff frequency Circuits Digital signal processing Delays Field programmable gate arrays |
| Language | English |
| License | https://creativecommons.org/licenses/by-nc-nd/4.0 Attribution: http://creativecommons.org/licenses/by |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c443t-746643a129de6ed71b036a45d993cdc477369fc06b4753d22ddd19d2f4421b4c3 |
| Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ORCID | 0000-0002-0021-5808 0000-0001-8630-2971 0000-0001-9639-1648 0000-0001-8076-6695 |
| OpenAccessLink | https://doaj.org/article/ac4d246ee3714de1b5b59d39d6490c57 |
| PQID | 3059517277 |
| PQPubID | 4845423 |
| PageCount | 1 |
| ParticipantIDs | hal_primary_oai_HAL_hal_04596488v1 doaj_primary_oai_doaj_org_article_ac4d246ee3714de1b5b59d39d6490c57 ieee_primary_10534772 crossref_citationtrail_10_1109_ACCESS_2024_3403033 crossref_primary_10_1109_ACCESS_2024_3403033 proquest_journals_3059517277 |
| PublicationCentury | 2000 |
| PublicationDate | 2024-01-01 |
| PublicationDateYYYYMMDD | 2024-01-01 |
| PublicationDate_xml | – month: 01 year: 2024 text: 2024-01-01 day: 01 |
| PublicationDecade | 2020 |
| PublicationPlace | Piscataway |
| PublicationPlace_xml | – name: Piscataway |
| PublicationTitle | IEEE access |
| PublicationTitleAbbrev | Access |
| PublicationYear | 2024 |
| Publisher | IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher_xml | – name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| References | ref13 ref35 ref12 ref34 ref15 ref37 ref14 ref36 ref31 ref30 ref11 ref33 ref10 ref32 ref2 ref1 ref17 ref39 (ref44) 2016 ref16 ref38 ref19 ref18 ref24 ref23 ref26 ref25 ref20 ref42 ref41 ref22 ref21 ref28 ref27 ref29 ref8 ref7 ref9 ref3 ref6 ref5 Lei (ref4) 2012; 6 ref40 (ref43) 2020 |
| References_xml | – ident: ref39 doi: 10.1038/s41598-020-74351-y – ident: ref36 doi: 10.1109/MMM.2020.3035862 – volume-title: PMODDA2T Reference Manual year: 2016 ident: ref44 – ident: ref9 doi: 10.1109/TCSI.2014.2361035 – ident: ref38 doi: 10.1080/03091902.2021.1967490 – ident: ref14 doi: 10.1016/j.vlsi.2023.02.005 – ident: ref6 doi: 10.1109/TVT.2020.3018817 – ident: ref42 doi: 10.1007/s11265-020-01575-6 – ident: ref5 doi: 10.1109/HST.2017.7951829 – ident: ref22 doi: 10.1587/elex.16.20190010 – ident: ref20 doi: 10.1109/LMWC.2017.2711572 – ident: ref25 doi: 10.1007/s10470-021-01826-x – ident: ref3 doi: 10.1109/MCOM.011.2000863 – ident: ref27 doi: 10.1016/j.physleta.2019.07.015 – ident: ref28 doi: 10.12720/ijsps.2.2.132-138 – ident: ref32 doi: 10.1109/ACCESS.2022.3226514 – ident: ref31 doi: 10.1103/PhysRevE.103.L020401 – ident: ref13 doi: 10.5539/apr.v3n2p81 – ident: ref15 doi: 10.1119/1.18813 – volume: 6 start-page: 1037 issue: 3 year: 2012 ident: ref4 article-title: Effect of group delay on channel estimation performance in OFDM system publication-title: Appl. Math. Inf. Sci. – ident: ref7 doi: 10.1109/MWSCAS.2009.5236044 – ident: ref17 doi: 10.1109/JSTQE.2002.807979 – ident: ref23 doi: 10.1109/TCAD.2021.3136982 – ident: ref40 doi: 10.1109/TCSII.2020.3012869 – ident: ref10 doi: 10.1109/TCSI.2015.2395631 – ident: ref18 doi: 10.1002/cta.1902 – ident: ref19 doi: 10.1063/1.5052497 – ident: ref26 doi: 10.2528/PIERC22011705 – ident: ref35 doi: 10.1109/TIE.2023.3321988 – ident: ref21 doi: 10.1109/TCSI.2021.3055416 – ident: ref30 doi: 10.1109/TIE.2022.3213904 – volume-title: 7 Series FPGAS and ZYNQ-7000 All Programmable Soc XADC Dual 12-bit 1-MSPS Analogto-Digital Converter User Guide (UG480) year: 2020 ident: ref43 – ident: ref24 doi: 10.1016/j.jestch.2023.101590 – ident: ref37 doi: 10.1080/03091902.2020.1799097 – ident: ref16 doi: 10.1016/S0375-9601(97)00244-2 – ident: ref34 doi: 10.1109/JSEN.2023.3342219 – ident: ref11 doi: 10.1109/TPEL.2017.2691062 – ident: ref2 doi: 10.1103/PhysRevApplied.9.034011 – ident: ref41 doi: 10.1016/B978-0-12-386914-2.00015-7 – ident: ref1 doi: 10.1109/TCSII.2014.2387615 – ident: ref33 doi: 10.1109/TCSII.2023.3276389 – ident: ref12 doi: 10.1080/00207721.2018.1443232 – ident: ref8 doi: 10.1109/TCSII.2014.2335437 – ident: ref29 doi: 10.1109/TIE.2021.3109543 |
| SSID | ssj0000816957 |
| Score | 2.320117 |
| Snippet | Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a... |
| SourceID | doaj hal proquest crossref ieee |
| SourceType | Open Website Open Access Repository Aggregation Database Enrichment Source Index Database Publisher |
| StartPage | 1 |
| SubjectTerms | Circuits Cross correlation Cutoff frequency Delays Digital NGD design Digital signal processing Embedded systems Engineering Sciences Field programmable gate arrays Finite impulse response filters FIR filters FIR-Based NGD Group delay Methodology NGD FPGA NGD implementation Signal Processing Time domain analysis Time-frequency analysis Waveforms |
| SummonAdditionalLinks | – databaseName: IEEE Electronic Library (IEL) dbid: RIE link: http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NT9wwEB0VxKE9FGipmvKhqOqxoev4I_GBw7KwcGhXHFqJm7X2TFokulvBsr-fsWNWoIpKlXKwIjuy_caeZ8d-A_DJE7ZGTk3lW2kqRSQqr21XtdiGwI_mMZWCTTSTSXt5aS_yZfV0F4aI0uEzOozJ9C8f5-EubpXxCNdSMR1cg7WmMf1lrdWGSowgYXWTlYXEwH4ZjkbcCF4D1upQKrZmKZ94nyTSzz7lVzwCmWKr_DUhJy8z3vzP-m3B60wny2GP_za8oNkbePVIZPAtHE3mS7ou8epnjA9STs5Oym8pbHTaUC-ZtJbji7NhFf0Zlqe_uV-RE1nKfAd-jE-_j86rHDShCkrJRdVEvXg5ZTeOZAgb4dlHTZVGJiIBA1dPGtuFgfGKVypY14goLNadUrXwKsh3sD6bz-g9lKoVnZAt4-VJad8ynF1AZgiaSZsPvoD6oTNdyIriMbDFtUsri4F1PQIuIuAyAgV8XhX60wtq_Dv7cURplTWqYacX3PEuDy43DQprZYii_CCS8JrtDaVFo-wg6KaAj4zxk2-cD7-6-I4ZrTU8iS1FATsR0UeV6sEsYO_BJlwe37eOZ0mmpsz9mg_PFNuFl7Ed_W7NHqwvbu5oHzbCcnF1e3OQTPceM83o_Q priority: 102 providerName: IEEE |
| Title | Novel digital NGD Methodology for FPGA-based Embedded Systems |
| URI | https://ieeexplore.ieee.org/document/10534772 https://www.proquest.com/docview/3059517277 https://hal.science/hal-04596488 https://doaj.org/article/ac4d246ee3714de1b5b59d39d6490c57 |
| Volume | 12 |
| WOSCitedRecordID | wos001231420400001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVAON databaseName: DOAJ Open Access Full Text customDbUrl: eissn: 2169-3536 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0000816957 issn: 2169-3536 databaseCode: DOA dateStart: 20130101 isFulltext: true titleUrlDefault: https://www.doaj.org/ providerName: Directory of Open Access Journals – providerCode: PRVHPJ databaseName: ROAD: Directory of Open Access Scholarly Resources customDbUrl: eissn: 2169-3536 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0000816957 issn: 2169-3536 databaseCode: M~E dateStart: 20130101 isFulltext: true titleUrlDefault: https://road.issn.org providerName: ISSN International Centre |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwrV1LT9wwEB5ViEM5VNCCSHkoqnpsII4fsQ8cdpddOJQVhyJxs9YehyLBUsGyR347YyesFiHBpVIURZZj2d-MPTOW_Q3ATxdQKz5RhdNcFSIEVjhpmkKj9p4eSXMqJZuox2N9eWnOl1J9xTNhLT1wC9zhxAushAohUsthYE5SW8gNKmFKL9M98rI2S8FUWoM1U0bWHc0QK81hbzCgEVFAWIkDLki1OX9lihJjPxmYv_E8ZEq08mZ1TiZntA5fOl8x77V93IBPYfoV1pYYBL_B0fhuHm7y4-urmPwjH58c52cpJ3TaLc_JI81H5ye9ok_GCvPhLYGG9NHxlG_CxWj4Z3BadBkRCi8EnxV1JIPnE7LRGFTAmjkyQBMhkbwMj17UNVem8aVygsIQrCpEZAarRoiKOeH5FqxM76ZhG3KhWcO4JmG4IKTTJKvGI5l_SR6Z8y6D6gUc6zu68Ji14samsKE0tkXURkRth2gGvxY__WvZMt6v3o-oL6pGqutUQApgOwWwHylABj9IZq_aOO39trGM3FWjaIWasww2o0iXOiU5oVVlsPsiY9tN3gdLSyD5neTY1d__Rwd34HMcdLtvswsrs_vHsAerfj67frjfT3pL77On4X66ffgMgSjtdQ |
| linkProvider | Directory of Open Access Journals |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3Pb9MwFH4aGxJwYAOKCPsVIY5kq-MfiQ87lG5dEV20w5B2s2o_ByaNFm1d_36eHa_ahEBCysGK7Mj29-z32bG_B_DReqwVn6rC1lwVwntWWKnbosbaOXokjakYbKJqmvryUp-ny-rxLoz3Ph4-8wchGf_l49zdha0yGuGSC6KDT2AjhM5K17VWWyohhoSWVdIWYn19OBgOqRm0CizFARdkz5w_8j9Rpp-8yo9wCDJGV_ljSo5-ZrT5nzXcgpeJUOaDzgJewZqfvYYXD2QG38BRM1_66xyvvocIIXlzepyfxcDRcUs9J9qaj85PB0XwaJif_KSeRUokMfMefBudXAzHRQqbUDgh-KKogmI8n5IjR688VsySl5oKiURFHDqqHle6dX1lBa1VsCwRkWksWyFKZoXjb2F9Np_5d5CLmrWM14SY9ULamgBtHRJHkETbrLMZlPedaVzSFA-hLa5NXFv0tekQMAEBkxDI4NOq0K9OUuPf2T8HlFZZgx52fEEdb9LwMlMnsBTK-yBAiJ5ZSRaHXKMSuu9klcEHwvjRN8aDiQnviNNqRdPYkmXQC4g-qFQHZgY79zZh0gi_NTRPEjkl9le9_0uxfXg2vjibmMmX5us2PA9t6vZudmB9cXPnd-GpWy6ubm_2ohn_BoCn7EY |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Novel+Digital+NGD+Methodology+for+FPGA-Based+Embedded+Systems&rft.jtitle=IEEE+access&rft.au=Rivo+Randriatsiferana&rft.au=Jordane+Lorandel&rft.au=Ruben+Salvador&rft.au=Christophe+Moy&rft.date=2024-01-01&rft.pub=IEEE&rft.eissn=2169-3536&rft.volume=12&rft.spage=71520&rft.epage=71534&rft_id=info:doi/10.1109%2FACCESS.2024.3403033&rft.externalDBID=DOA&rft.externalDocID=oai_doaj_org_article_ac4d246ee3714de1b5b59d39d6490c57 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=2169-3536&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=2169-3536&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=2169-3536&client=summon |