LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 42; H. 6; S. 2069 - 2073
Hauptverfasser:	Yan, Aibin, Li, Zhixing, Cui, Jie, Huang, Zhengfeng, Ni, Tianming, Girard, Patrick, Wen, Xiaoqing
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.06.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Algorithm-based verification Algorithms Electronic design automation Engineering Sciences Error recovery fault tolerance Feedback loop Feedback loops Feeds Integrated circuits Inverters latch design Latches Micro and nanotechnologies Microelectronics Muller C-element (MCE) multiple-node-upset (MNU) Nodes Recovery Switching circuits Transistors Verification Fault tolerance Algorithm-based verification Multiple-node-upset Muller C-element Latch design
ISSN:	0278-0070, 1937-4151
Online-Zugang:	Volltext
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