Test pattern optimization scheme based on Hybrid Ant Colony Optimization

The trend toward device miniaturization has made digital circuit testing both essential and increasingly complex. To achieve complete fault coverage, a large number of test patterns are applied, which leads to increased switching activity due to larger number of transitions between consecutive patte...

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Veröffentlicht in:Scientific reports Jg. 15; H. 1; S. 34453 - 18
Hauptverfasser: Asha Pon, S., Jeyalakshmi, V.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: London Nature Publishing Group UK 02.10.2025
Nature Publishing Group
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Schlagworte:
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Algorithms
Artificial intelligence
Circuits
Data compression
Feedback
Genetic algorithms
Humanities and Social Sciences
Hybrid ant colony optimization
KL divergence
Literature reviews
Methods
multidisciplinary
Neural networks
Optimization algorithms
Optimization techniques
Power consumption
Prim’s algorithm
Science
Science (multidisciplinary)
Test data reduction
Test pattern reordering
Transition count reduction
KL divergence
Prim’s algorithm
Hybrid ant colony optimization
Transition count reduction
Test data reduction
Test pattern reordering
ISSN:2045-2322, 2045-2322
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Zusammenfassung:The trend toward device miniaturization has made digital circuit testing both essential and increasingly complex. To achieve complete fault coverage, a large number of test patterns are applied, which leads to increased switching activity due to larger number of transitions between consecutive patterns. This rise in switching activity significantly elevates power consumption during testing. Therefore, minimizing transitions between test patterns is crucial for reducing test power. Optimizing test patterns by reducing their count and reordering them is an effective approach to lower switching activity. In this paper, Hybrid Ant Colony Optimization technique is proposed to reduce power consumption during sequential circuit testing. This approach integrates traditional Ant Colony Optimization with Kullback-Leibler divergence and Prim’s algorithm. The combination of Ant Colony Optimization and Kullback-Leibler divergence helps in reducing the number of test patterns based on the probability of ant traversal. The resulting patterns are then reordered using Prim’s algorithm to minimize transitions between them. Experimental evaluation reveals that the proposed methodology achieves a 71.60% reduction in transition count over the conventional Ant Colony Optimization algorithm on smaller ISCAS’89 benchmark circuits. Furthermore, it attains an average power reduction of 57.48% when compared to test patterns generated using a Linear Feedback Shift Register (LFSR), highlighting its effectiveness in low-power VLSI testing.
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ISSN:2045-2322
2045-2322
DOI:10.1038/s41598-025-17625-7