Integer Linear Programming Models for Global Routing

Modern integrated circuit design involves the layout of circuits consisting of millions of switching elements or transistors. Due to the sheer complexity of the problem, optimizing the connectivity between transistors is very difficult. The circuit interconnection is the single most important factor...

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Veröffentlicht in:INFORMS journal on computing Jg. 18; H. 2; S. 137 - 150
Hauptverfasser: Behjat, Laleh, Vannelli, Anthony, Rosehart, William
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Linthicum INFORMS 22.03.2006
Institute for Operations Research and the Management Sciences
Schlagworte:
Design and construction
Design engineering
global routing
Heuristic
Integer programming
Integrated circuit fabrication
Integrated circuits
Linear programming
linear relaxation
Methods
Semiconductor chips
Studies
Technology application
Transistors
Very-large-scale integration
VLSI layout
United States
ISSN:1091-9856, 1526-5528, 1091-9856
Online-Zugang:Volltext
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Zusammenfassung:Modern integrated circuit design involves the layout of circuits consisting of millions of switching elements or transistors. Due to the sheer complexity of the problem, optimizing the connectivity between transistors is very difficult. The circuit interconnection is the single most important factor in performance criteria such as signal delay, power dissipation, circuit size, and cost. These factors dictate that interconnections, i.e., wires, be made as short as possible. The wire-minimization problem is generally formulated as a sequence of discrete optimization subproblems that are known to be NP-hard. Hence, they can only be solved approximately using meta-heuristics. These methods are computationally expensive and the quality of the solution depends to a great extent on an appropriate choice of starting configuration and modeling techniques. In this paper, new modeling techniques are used to solve the routing problem formulated as an integer programming problem. The main contribution of this paper is a proposed global routing heuristic that combines the wire length, channel congestion, and number of pins in routes to find the best wiring layout of a circuit. By adding information such as channel congestion and the number of pins in each route as well as the wire length, the quality of the solution is improved. In addition, the solutions of the large relaxed linear programming problems are skewed towards a zero-one solution, resulting in faster convergence. The developed LP models in this paper are useful when solving the global routing problem for two reasons; first, the new interior-point algorithms to solve the LP problem are polynomial in time. Second, "near optimal wiring" is obtained in polynomial time without performing randomized rounding.
Bibliographie:SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 14
ISSN:1091-9856
1526-5528
1091-9856
DOI:10.1287/ijoc.1040.0127