An efficient crossover architecture for hardware parallel implementation of genetic algorithm

In this article a new architecture for hardware implementation of genetic algorithm in reconfigurable embedded systems is presented. The main idea is based on the efficient use of a genetic algorithm's crossover operator to enhance the speed of algorithm to reach an optimal solution. In this ar...

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Vydané v:Neurocomputing (Amsterdam) Ročník 128; s. 316 - 327
Hlavní autori: Faraji, Rasoul, Naji, Hamid Reza
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Amsterdam Elsevier B.V 27.03.2014
Elsevier
Predmet:
Algorithmics. Computability. Computer arithmetics
Algorithms
Applied sciences
Architecture
Architecture (computers)
Computer science; control theory; systems
Crossover operator
Crossovers
Exact sciences and technology
FPGA
Genetic algorithm
Genetic algorithms
Hardware
Operators
Optimization
Theoretical computing
Genetic algorithm
FPGA
Crossover operator
Optimal algorithm
Reuse
Field programmable gate array
Optimization
Circuit architecture
Boarded computer
Optimal solution
Problem solving
Parallelism
Reconfigurable architectures
ISSN:0925-2312, 1872-8286
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Popis
Shrnutí:In this article a new architecture for hardware implementation of genetic algorithm in reconfigurable embedded systems is presented. The main idea is based on the efficient use of a genetic algorithm's crossover operator to enhance the speed of algorithm to reach an optimal solution. In this article a new crossover called DSO and also two new architectures for implementation of crossover operators are introduced to provide suitable solutions for solving the problems related to fitness function of the genetic algorithm. At first, some optimum operators are selected and then utilized in a new parallel architecture to increase the speed and accuracy of algorithm convergence. Finally, based on reusability of existing resources, the main idea of the article is introduced to improve the performance of the algorithm and finding the optimal solution. The properties of FPGAs such as flexibility and parallelism help this purpose.
Bibliografia:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0925-2312
1872-8286
DOI:10.1016/j.neucom.2013.08.035