On optimizing system energy of voltage–frequency island based 3-D multi-core SoCs under thermal constraints

Three dimensional (3-D) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage–frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2...

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Bibliographic Details
Published in:Integration (Amsterdam) Vol. 48; pp. 36 - 45
Main Authors: Jin, Song, Wang, Yu, Liu, Tongna
Format: Journal Article
Language:English
Published: Amsterdam Elsevier B.V 01.01.2015
Elsevier
Subjects:
3-Dimensional SoCs
Applied sciences
Circuit properties
Design engineering
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Islands
Optimization
Partitioning
Platforms
Power balancing
Reduction
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
System energy
Task scheduling
Thermal constraint
Three dimensional
Voltage–frequency island
Voltage–frequency island
Power balancing
Thermal constraint
System energy
3-Dimensional SoCs
Interconnection network
State of the art
Partition method
Stacking
Voltage-frequency island
Network architecture
Mapping
Implementation
Optimization
Partitioning
Three dimensional structure
Electric power consumption
Minimum energy
Globally asynchronous locally synchronous
Task scheduling
System on a chip
Algorithm
Energy savings
Multicore processor
Three dimensional model
Integrated circuit
Low-power electronics
ISSN:0167-9260, 1872-7522
Online Access:Get full text
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Summary:Three dimensional (3-D) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage–frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2-D platform, which cannot handle the exacerbated thermal issues and the increased solution space from 3-D integration. In this paper, we propose an optimization framework targeting VFI-based 3-D multi-core SoCs to minimize system energy meanwhile still meeting task deadline and thermal constraints. Our framework conducts at an earlier design phase in which designers have the freedom to determine the core stacks and map them into the hardware platform. Besides energy-aware task scheduling, we also conduct core stacking and task adjusting to balance the powers across the chip for thermal optimization. Moreover, by treating each core stack as a unity, the complicated problem of core mapping and VFI partitioning in 3-D platform can be simplified as a 2-D one. Experimental results demonstrate that on average our framework can achieve an energy reduction of 15.8% over the prior thermal balancing algorithm [17] (X. Zhou, J. Yang, Y. Xu, et al. Thermal-aware task scheduling for 3D multicore processors, IEEE Trans. Parallel Distrib. Syst. (TPDS), 21(1) (2010), 60–71.). Moreover, on average a reduction of 4.8°C in peak temperature is achieved by our framework, compared with the state-of-the-art energy optimization scheme [8] (U.Y. Ogras, R. Marculescu, P. Choudhary, et al. Voltage–frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110–115.). •We unified consider task scheduling and V/F scaling to minimize computation energy.•Core stacking and task migrating are performed to balance powers across the chip.•We simplify 3-D mapping problem into a 2-D one by treating core stack as a unity.
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ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2014.05.001