High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and In...

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Veröffentlicht in:	IEEE transactions on computers Jg. 69; H. 4; S. 534 - 548
Hauptverfasser:	Ueno, Rei, Homma, Naofumi, Morioka, Sumio, Miura, Noriyuki, Matsuda, Kohei, Nagata, Makoto, Bhasin, Shivam, Mathieu, Yves, Graba, Tarik, Danger, Jean-Luc
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.04.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Institute of Electrical and Electronics Engineers
Schlagworte:	AES Algorithms Computer architecture Computer Arithmetic Computer Science Critical path Cryptography and Security Data paths Delay Delays Digital Libraries Electronics Encryption Energy consumption Engineering Sciences Hardware Hardware Architecture hardware architectures Logic gates Logic synthesis Modeling and Simulation Optimization Optimization techniques Poles and towers Power consumption round-based encryption architecture unified encryption/decryption architecture
ISSN:	0018-9340, 1557-9956
Online-Zugang:	Volltext
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