All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition

This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not requi...

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Veröffentlicht in:IEEE transactions on circuits and systems. II, Express briefs Jg. 63; H. 1; S. 99 - 103
Hauptverfasser: Han Le Duc, Duc Minh Nguyen, Jabbour, Chadi, Graba, Tarik, Desgreys, Patricia, Jamin, Olivier, Van Tam Nguyen
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.01.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Institute of Electrical and Electronics Engineers
Schlagworte:
Algorithms
Calibration
Circuits
Convergence
Depletion
Digital circuits
Dissipation
Electronics
Engineering Sciences
Finite impulse response filters
FPGA/ASIC implementation
Niobium
polyphase filtering
Sampling
Time measurements
Time-frequency analysis
Timing
Timing skews calibration
Undersampling TIADCs
timing skew calibration
polyphase filtering
undersampling time-interleaved analog-to-digital converters (TIADCs)
Field-programmable gate array (FPGA)/application-specific-integrated-circuit (ASIC) implementation
ISSN:1549-7747, 1558-3791
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm 2 and dissipates the total power of 41 mW.
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ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2015.2483423