A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders

High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. This paper proposes an efficient very large scale integration architecture for integer multi-resolut...

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Vydáno v:	IEEE transactions on circuits and systems for video technology Ročník 20; číslo 9; s. 1242 - 1254
Hlavní autoři:	Yin, Haibing, Jia, Huizhu, Qi, Honggang, Ji, Xianghu, Xie, Xiaodong, Gao, Wen
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York, NY IEEE 01.09.2010 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Algorithms Applied sciences Architecture audio video coding standard (AVS) Bandwidth Circuit properties Coders Coding Coding standards Design. Technologies. Operation analysis. Testing Digital broadcasting Electric, optical and optoelectronic circuits Electronic circuits Electronics Encoders Exact sciences and technology H.264 Hardware High definition High definition video Image processing Information, signal and communications theory Integers Integrated circuits Integrated circuits by function (including memories and processors) Motion control Motion estimation multi-resolution motion estimation Parallel processing Polyethylenes Random access memory Rate-distortion Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors Signal processing Telecommunications and information theory Throughput Very large scale integration very large scale integration (VLSI) video coding Video coding Signal compression High resolution Processor Image processing H.264 Information rate Multiresolution analysis Implementation Optimization Video signal processing Block matching Data flow AVS standard Traffic control Parallel processing audio video coding standard (AVS) Multilevel system VLSI circuit Motion estimation Architecture Coding circuit Flow rate regulation Reuse Teletraffic Buffer system Algorithm Information transmission Circuit architecture very large scale integration (VLSI) Signal processing multi-resolution motion estimation
ISSN:	1051-8215, 1558-2205
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