A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders

High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. This paper proposes an efficient very large scale integration architecture for integer multi-resolut...

Celý popis

Uloženo v:

Podrobná bibliografie
Vydáno v:	IEEE transactions on circuits and systems for video technology Ročník 20; číslo 9; s. 1242 - 1254
Hlavní autoři:	Yin, Haibing, Jia, Huizhu, Qi, Honggang, Ji, Xianghu, Xie, Xiaodong, Gao, Wen
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York, NY IEEE 01.09.2010 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Algorithms Applied sciences Architecture audio video coding standard (AVS) Bandwidth Circuit properties Coders Coding Coding standards Design. Technologies. Operation analysis. Testing Digital broadcasting Electric, optical and optoelectronic circuits Electronic circuits Electronics Encoders Exact sciences and technology H.264 Hardware High definition High definition video Image processing Information, signal and communications theory Integers Integrated circuits Integrated circuits by function (including memories and processors) Motion control Motion estimation multi-resolution motion estimation Parallel processing Polyethylenes Random access memory Rate-distortion Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors Signal processing Telecommunications and information theory Throughput Very large scale integration very large scale integration (VLSI) video coding Video coding Signal compression High resolution Processor Image processing H.264 Information rate Multiresolution analysis Implementation Optimization Video signal processing Block matching Data flow AVS standard Traffic control Parallel processing audio video coding standard (AVS) Multilevel system VLSI circuit Motion estimation Architecture Coding circuit Flow rate regulation Reuse Teletraffic Buffer system Algorithm Information transmission Circuit architecture very large scale integration (VLSI) Signal processing multi-resolution motion estimation
ISSN:	1051-8215, 1558-2205
On-line přístup:	Získat plný text
Tagy:	Přidat tag Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!

Popis
Shrnutí:	High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. This paper proposes an efficient very large scale integration architecture for integer multi-resolution motion estimation based on optimized algorithm. There are three major contributions in this paper. First, this paper proposes a hardware friendly multi-resolution motion estimation algorithm well-suited for high definition video encoder. Second, parallel processing element (PE) array structure is proposed to implement three-level hierarchical motion estimation, only 256PEs are enough for one reference frame real-time high definition motion estimation by efficient PE reuse. Third, efficient on-chip reference pixel buffer sharing mechanism between integer and fractional motion estimation is proposed with almost 50% SRAM saving and memory bandwidth reduction. The proposed multi-resolution motion estimation algorithm reached a good balance between complexity and performance with rate distortion optimized variable block size motion estimation support. Also, we have achieved moderate logic circuit and on-chip SRAM consumption. The proposed architecture is well-suited for all MPEG-like video coding standards such as H.264, audio video coding standard, and VC-1.
Bibliografie:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 content type line 23
ISSN:	1051-8215 1558-2205
DOI:	10.1109/TCSVT.2010.2058476