Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE

Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders th...

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Vydané v:IEEE journal of solid-state circuits Ročník 46; číslo 1; s. 8 - 17
Hlavní autori: Studer, C, Benkeser, C, Belfanti, S, Quiting Huang
Médium: Journal Article Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: New York, NY IEEE 01.01.2011
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
3G mobile communication
Applied sciences
ASIC implementation
Circuit properties
Circuits
CMOS
Consumption
Decoding
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Evolution
Exact sciences and technology
Integrated circuits
low-power
LTE
Memory management
Multiaccess communication
parallel turbo-decoder
Power consumption
radix-4
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Systematics
Tasks
Throughput
Wireless communication
Performance evaluation
low-power
3G mobile communication
ASIC implementation
Decoding circuit
Turbo code
parallel turbo-decoder
Computational complexity
Implementation
radix-4
Complementary MOS technology
Integrated circuit
Electric power consumption
Low-power electronics
LTE
Custom circuit
ISSN:0018-9200, 1558-173X
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Shrnutí:Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. To highlight the effectiveness of our design-approach, we realized a 3.57 mm 2 radix-4based 8× parallel turbo-decoder ASIC in 0.13 μm CMOS technology achieving 390 Mb/s. At the more realistic 100 Mb/s LTE milestone targeted by industry today, the turbo-decoder consumes only 69 mW.
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2010.2075390