An Efficient and Scalable Semiconductor Architecture for Parallel Automata Processing

We present the design and development of the automata processor, a massively parallel non-von Neumann semiconductor architecture that is purpose-built for automata processing. This architecture can directly implement non-deterministic finite automata in hardware and can be used to implement complex...

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Bibliographic Details
Published in:	IEEE transactions on parallel and distributed systems Vol. 25; no. 12; pp. 3088 - 3098
Main Authors:	Dlugosch, Paul, Brown, Dave, Glendenning, Paul, Leventhal, Michael, Noyes, Harold
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.12.2014 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	accelerator architectures Architecture (computers) Arrays Automata Biology Complexity theory Computer information security Hardware high performance computing Mathematical analysis Microprocessors parallel architectures Radiation detectors reconfigurable architectures Routing Semiconductors Transaction processing
ISSN:	1045-9219, 1558-2183
Online Access:	Get full text
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