A scalable high-performance computing solution for networks on chips

The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs.

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE MICRO Jg. 22; H. 5; S. 46 - 55
1. Verfasser: Forsell, M.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Los Alamitos IEEE 01.09.2002
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Computation
Computer architecture
Concurrent computing
Design engineering
Design methodology
Interconnection
Mathematical models
Microprocessors
Network-on-a-chip
Networks
Parallel processing
Parallel programming
Phase change random access memory
Processors
Semiconductors
Synchronization
System on chip
System-on-a-chip
Systems design
ISSN:0272-1732, 1937-4143
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs.
Bibliographie:SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 14
ObjectType-Article-2
content type line 23
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2002.1044299