Block-based multiperiod dynamic memory design for low data-retention power

Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 11; no. 6; pp. 1006 - 1018
Main Authors: Joohee Kim, Papaefthymiou, M.C.
Format: Journal Article
Language:English
Published: Piscataway, NJ IEEE 01.12.2003
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Applied sciences
Blocking
Computational modeling
Degradation
Design. Technologies. Operation analysis. Testing
Dissipation
Distributed computing
Dynamic random access memory
Dynamics
Electronics
Exact sciences and technology
Handheld computers
Integrated circuits
Integrated circuits by function (including memories and processors)
Leakage
Magnetic and optical mass memories
Polynomials
Portable computers
Power dissipation
Process design
Random access memory
Robustness
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Storage and reproduction of information
Studies
Very large scale integration
dynamic memory
Memory devices
Index Terms-Algorithm design
High density
Random access memory
Dynamical storage
Algorithm
block-based multiperiod refresh
Implementation
Polynomial time
Computation time
Energy dissipation
Integrated circuit
Recording density
DRAM chips
Portable equipment
low-power design
Low-power electronics
low-energy design
process variations tolerance
ISSN:1063-8210, 1557-9999
Online Access:Get full text
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Description
Summary:Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN/sup 2/) steps our algorithm computes K refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2003.817524