Low-complexity CRC-aided early stopping unit for parallel turbo decoder
A low-complexity distributed cyclic redundancy check (CRC) architecture for the CRC-aided early stopping unit is proposed. In the previous distributed CRC unit, the general high-order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high-hardware cost and long criti...
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| Veröffentlicht in: | Electronics letters Jg. 51; H. 21; S. 1660 - 1662 |
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The Institution of Engineering and Technology
08.10.2015
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| Abstract | A low-complexity distributed cyclic redundancy check (CRC) architecture for the CRC-aided early stopping unit is proposed. In the previous distributed CRC unit, the general high-order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high-hardware cost and long critical path-delay. Accordingly, a computation algorithm based on GF arithmetic is analysed and an optimal CRC unit with the small order of the GF multiplier and newly designed linear feedback shift register is proposed. The proposed CRC architecture is implemented in 65 nm CMOS process for radix-22 and radix-24 parallel turbo decoders based on LTE-Advanced. In the radix-22 system, reductions of about 57.1% of gate count, 31.7% of critical path-delay and 44.1% of power consumption are achieved compared with the previous work. |
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| AbstractList | A low‐complexity distributed cyclic redundancy check (CRC) architecture for the CRC‐aided early stopping unit is proposed. In the previous distributed CRC unit, the general high‐order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high‐hardware cost and long critical path‐delay. Accordingly, a computation algorithm based on GF arithmetic is analysed and an optimal CRC unit with the small order of the GF multiplier and newly designed linear feedback shift register is proposed. The proposed CRC architecture is implemented in 65 nm CMOS process for radix‐22 and radix‐24 parallel turbo decoders based on LTE‐Advanced. In the radix‐22 system, reductions of about 57.1% of gate count, 31.7% of critical path‐delay and 44.1% of power consumption are achieved compared with the previous work. A low-complexity distributed cyclic redundancy check (CRC) architecture for the CRC-aided early stopping unit is proposed. In the previous distributed CRC unit, the general high-order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high-hardware cost and long critical path-delay. Accordingly, a computation algorithm based on GF arithmetic is analysed and an optimal CRC unit with the small order of the GF multiplier and newly designed linear feedback shift register is proposed. The proposed CRC architecture is implemented in 65 nm CMOS process for radix-2 super(2) and radix-2 super(4) parallel turbo decoders based on LTE-Advanced. In the radix-2 super(2) system, reductions of about 57.1% of gate count, 31.7% of critical path-delay and 44.1% of power consumption are achieved compared with the previous work. A low‐complexity distributed cyclic redundancy check (CRC) architecture for the CRC‐aided early stopping unit is proposed. In the previous distributed CRC unit, the general high‐order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high‐hardware cost and long critical path‐delay. Accordingly, a computation algorithm based on GF arithmetic is analysed and an optimal CRC unit with the small order of the GF multiplier and newly designed linear feedback shift register is proposed. The proposed CRC architecture is implemented in 65 nm CMOS process for radix‐2 2 and radix‐2 4 parallel turbo decoders based on LTE‐Advanced. In the radix‐2 2 system, reductions of about 57.1% of gate count, 31.7% of critical path‐delay and 44.1% of power consumption are achieved compared with the previous work. A low-complexity distributed cyclic redundancy check (CRC) architecture for the CRC-aided early stopping unit is proposed. In the previous distributed CRC unit, the general high-order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high-hardware cost and long critical path-delay. Accordingly, a computation algorithm based on GF arithmetic is analysed and an optimal CRC unit with the small order of the GF multiplier and newly designed linear feedback shift register is proposed. The proposed CRC architecture is implemented in 65 nm CMOS process for radix-22 and radix-24 parallel turbo decoders based on LTE-Advanced. In the radix-22 system, reductions of about 57.1% of gate count, 31.7% of critical path-delay and 44.1% of power consumption are achieved compared with the previous work. |
| Author | Kim, Ji-Hoon Kim, Hyeji Lee, Youngjoo |
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| Cites_doi | 10.1109/TCSII.2015.2435131 10.1109/WCL.2013.052813.130259 10.1109/TC.2003.1234528 10.1109/4234.864187 |
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| Keywords | parallel turbo decoder optimal CRC unit low-complexity distributed cyclic redundancy check architecture CMOS process Galois fields linear feedback shift register turbo codes LTE-advanced low-complexity CRC-aided early stopping unit general high-order Galois field multiplier cyclic redundancy check codes shift registers CMOS integrated circuits Long Term Evolution |
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| References | Wei, Y.; Jiang, M.; Xia, B. (C3) 2013; 2 Wu, Y.; Woerner, B.D.; Ebel, W.J. (C1) 2000; 4 Kim, H.; Choi, I.; Byun, W. (C5) 2015; 62 Campobello, G.; Patané, G.; Russo, M. (C4) 2003; 52 2000; 4 2015; 62 2003; 52 2013; 2 2013 e_1_2_8_3_1 e_1_2_8_2_1 e_1_2_8_5_1 e_1_2_8_4_1 Belfanti S. (e_1_2_8_7_1) 2013 e_1_2_8_6_1 |
| References_xml | – volume: 4 start-page: 258 issue: 8 year: 2000 end-page: 260 ident: C1 article-title: A simple stopping criterion for turbo decoding publication-title: IEEE Trans. Commun. Lett. – volume: 2 start-page: 471 issue: 5 year: 2013 end-page: 474 ident: C3 article-title: A CRC-aided hybrid decoding algorithm for turbo codes publication-title: IEEE Wirel. Commun. Lett. – volume: 62 start-page: 906 issue: 9 year: 2015 end-page: 910 ident: C5 article-title: Distributed CRC architecture for high-radix parallel turbo decoding in LTE-advanced publication-title: IEEE Trans. Circuits Syst. II – volume: 52 start-page: 1312 issue: 10 year: 2003 end-page: 1319 ident: C4 article-title: Parallel CRC realization publication-title: IEEE Trans. Comput. – volume: 2 start-page: 471 issue: 5 year: 2013 end-page: 474 article-title: A CRC‐aided hybrid decoding algorithm for turbo codes publication-title: IEEE Wirel. Commun. Lett. – start-page: C284 year: 2013 end-page: C285 – volume: 62 start-page: 906 issue: 9 year: 2015 end-page: 910 article-title: Distributed CRC architecture for high‐radix parallel turbo decoding in LTE‐advanced publication-title: IEEE Trans. Circuits Syst. II – volume: 52 start-page: 1312 issue: 10 year: 2003 end-page: 1319 article-title: Parallel CRC realization publication-title: IEEE Trans. Comput. – volume: 4 start-page: 258 issue: 8 year: 2000 end-page: 260 article-title: A simple stopping criterion for turbo decoding publication-title: IEEE Trans. Commun. Lett. – ident: e_1_2_8_6_1 doi: 10.1109/TCSII.2015.2435131 – ident: e_1_2_8_4_1 doi: 10.1109/WCL.2013.052813.130259 – ident: e_1_2_8_3_1 – ident: e_1_2_8_5_1 doi: 10.1109/TC.2003.1234528 – ident: e_1_2_8_2_1 doi: 10.1109/4234.864187 – start-page: C284 volume-title: A 1 Gbps LTE‐advanced turbo‐decoder ASIC in 65 nm CMOS year: 2013 ident: e_1_2_8_7_1 |
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| Snippet | A low-complexity distributed cyclic redundancy check (CRC) architecture for the CRC-aided early stopping unit is proposed. In the previous distributed CRC... A low‐complexity distributed cyclic redundancy check (CRC) architecture for the CRC‐aided early stopping unit is proposed. In the previous distributed CRC... |
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| SubjectTerms | Architecture CMOS CMOS integrated circuits CMOS process Counting cyclic redundancy check codes Decoders Galois fields general high‐order Galois field multiplier Information and communications linear feedback shift register Linear feedback shift registers Long Term Evolution low‐complexity CRC‐aided early stopping unit low‐complexity distributed cyclic redundancy check architecture LTE‐advanced Multipliers optimal CRC unit Optimization parallel turbo decoder Power consumption shift registers turbo codes |
| Title | Low-complexity CRC-aided early stopping unit for parallel turbo decoder |
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