Low-complexity CRC-aided early stopping unit for parallel turbo decoder

A low-complexity distributed cyclic redundancy check (CRC) architecture for the CRC-aided early stopping unit is proposed. In the previous distributed CRC unit, the general high-order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high-hardware cost and long criti...

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Vydáno v:	Electronics letters Ročník 51; číslo 21; s. 1660 - 1662
Hlavní autoři:	Kim, Hyeji, Lee, Youngjoo, Kim, Ji-Hoon
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	The Institution of Engineering and Technology 08.10.2015
Témata:	Architecture CMOS CMOS integrated circuits CMOS process Counting cyclic redundancy check codes Decoders Galois fields general high‐order Galois field multiplier Information and communications linear feedback shift register Linear feedback shift registers Long Term Evolution low‐complexity CRC‐aided early stopping unit low‐complexity distributed cyclic redundancy check architecture LTE‐advanced Multipliers optimal CRC unit Optimization parallel turbo decoder Power consumption shift registers turbo codes parallel turbo decoder optimal CRC unit low-complexity distributed cyclic redundancy check architecture CMOS process Galois fields linear feedback shift register turbo codes LTE-advanced low-complexity CRC-aided early stopping unit general high-order Galois field multiplier cyclic redundancy check codes shift registers CMOS integrated circuits Long Term Evolution
ISSN:	0013-5194, 1350-911X, 1350-911X
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Popis
Shrnutí:	A low-complexity distributed cyclic redundancy check (CRC) architecture for the CRC-aided early stopping unit is proposed. In the previous distributed CRC unit, the general high-order Galois field (GF) multiplier occupies almost the area of the CRC unit and requires high-hardware cost and long critical path-delay. Accordingly, a computation algorithm based on GF arithmetic is analysed and an optimal CRC unit with the small order of the GF multiplier and newly designed linear feedback shift register is proposed. The proposed CRC architecture is implemented in 65 nm CMOS process for radix-22 and radix-24 parallel turbo decoders based on LTE-Advanced. In the radix-22 system, reductions of about 57.1% of gate count, 31.7% of critical path-delay and 44.1% of power consumption are achieved compared with the previous work.
Bibliografie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23
ISSN:	0013-5194 1350-911X 1350-911X
DOI:	10.1049/el.2015.2262