Semiconductor Manufacturing Final Test Yield Optimization and Wafer Acceptance Test Parameter Inverse Design Using Multi-Objective Optimization Algorithms

In the semiconductor industry, many previous optimization studies have been carried out at the integrated circuit front-end design phase to identify optimal circuit elements' size and design parameters. With the scaling of device dimensions, semiconductor manufacturing back-end Final Test (FT)...

Celý popis

Uložené v:

Podrobná bibliografia
Vydané v:	IEEE access Ročník 9; s. 137655 - 137666
Hlavní autori:	Jiang, Dan, Lin, Weihua, Raghavan, Nagarajan
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Piscataway IEEE 2021 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Acceptance tests Algorithms Biological system modeling Circuit design CMOS Design optimization Design parameters Fabrication final test Integrated circuits Inverse design Machine learning Manufacturing Mathematical models multi-objective optimization Multiple objective analysis Optimization Optimization algorithms Parameter identification Prediction algorithms process variation Production Random processes Semiconductor device modeling Semiconductor manufacturing smart manufacturing yield prediction
ISSN:	2169-3536, 2169-3536
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!

Buďte prvý, kto okomentuje tento záznam!